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US 2020/0395318 A1Published application
3d trench reference planes for integrated-circuit die packages
AssigneeIntel Corporation
InventorsChin Lee Kuan, Jackson Chung Peng Kong, Bok Eng Cheah
Life of this patent
Estimating the term…
Abstract
A voltage-reference plane has gradient regions that provide altered thicknesses that are useful in a power-deliver network for a semiconductor package substrate. Different signal trace types are located over various portions of the gradient regions to facilitate signal integrity.
Claims25
A semiconductor package substrate, comprising:
- a package substrate including a die side and a land side;
- a first voltage reference plane in the package substrate, wherein the first voltage-reference plane has a first thickness;
- a second voltage-reference plane in the package substrate, wherein the second voltage-reference plane has a second thickness, wherein the first and second voltage-reference planes occupy at least some of the same Z-height in the package substrate;
- and
- at least one trace above the voltage-reference planes.
2 more elements
An integrated-circuit package substrate, comprising:
- a package substrate including a die side and a land side;
- a first bottom voltage reference plane in the package substrate, wherein the first bottom voltage-reference plane has a first thickness;
- a second bottom voltage-reference plane in the package substrate and isolated from the first bottom voltage-reference plane, wherein the second bottom voltage-reference plane has a second thickness, wherein the first and second bottom voltage-reference planes occupy at least some of the same Z-height in the package substrate;
- at least one trace above the voltage-reference planes;
- a first top voltage-reference plane stacked above the first bottom voltage reference plane;
- a second top voltage-reference plane stacked above the second bottom voltage-reference plane and isolated from the first top voltage-reference plane within the semiconductor package substrate;
- and
- at least one signal trace above one of the first and second top voltage reference planes.
5 more elements
An integrated-circuit package substrate, comprising:
- a package substrate including a die side and a land side;
- a functional core section including four voltage planes spaced apart by dielectric layers;
- a first top voltage plane below the die side;
- a second top voltage plane spaced apart from the first top voltage plane by a dielectric layer, wherein the second top voltage plane has a greater thickness than the first top voltage plane;
- a third top voltage plane spaced apart from the second top voltage plane by a dielectric layer, wherein the third top voltage plane is spaced apart and adjacent by a voltage plane in the functional core section;
- a first bottom voltage plane above the land side;
- a second bottom voltage plane spaced apart from the first bottom voltage plane by a dielectric layer, wherein the second bottom voltage plane has a greater thickness than the first bottom voltage plane;
- a third bottom voltage plane spaced apart from the second bottom voltage plane by a dielectric layer, wherein the third bottom voltage plane is spaced apart and adjacent a voltage plane in the functional core section.
5 more elements
Dependencies are inferred from the claim text.