US 2020/0395294 A1 · BACK END OF LINE (BEOL) TIME DEPENDENT DIELECTRIC BREAKDOWN (TDDB) MITIGATION WITHIN A VERTICAL INTERCONNECT ACCESS (VIA) LEVEL OF AN INTEGRATED CIRCUIT (IC) DEVICE

Abstract

An IC device, such as a wafer, chip, die, processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), or the like include a chamfered VIA that connects an upper wiring line and a first lower wiring line. The chamfered VIA includes a chamfer or fillet upon the edge that connects the VIA sidewall(s) with the VIA contact surface that is connected to the first lower wiring line. The chamfer or fillet effectively increases the amount of a dielectric material, such as a high-k dielectric material, within a trench of the VIA and that is between the chamfered VIA and a second lower wiring line that neighbors the first lower wiring line. This increased dielectric material improves TDDB between the chamfered VIA and the second lower wiring line and mitigates TDDB effects, such as electrical shorts between the chamfered VIA and the second lower wiring line.

Claims15

Dependent claims

An integrated circuit (IC) device fabrication method comprising:

forming a lower wiring line within a lower wiring level;
forming an upper wiring line trench and a chamfered vertical interconnect access (VIA) trench within an upper wiring level, the chamfered VIA trench comprising a vertical sidewall and a chamfered surface connected to the vertical sidewall, the chamfered VIA trench exposing at least a portion of the lower wiring line there below;
forming a monolayer upon the exposed portion of the lower wiring line within the VIA trench;
forming a dielectric film layer upon the vertical sidewall and the chamfered surface within the VIA trench;
removing the monolayer from the VIA trench to re-expose the portion of the lower wiring line while retaining the dielectric film layer upon the vertical sidewall and upon the chamfered surface within the VIA trench;
and
forming a chamfered VIA within the chamfered VIA trench at least upon the re-exposed portion of the lower wiring line.

4 more elements

An integrated circuit (IC) device fabrication method comprising:

forming a lower wiring line within a lower wiring level;
forming an upper wiring line trench and a chamfered vertical interconnect access (VIA) trench within an upper wiring level, the chamfered VIA trench comprising a vertical sidewall and a chamfered surface connected to the vertical sidewall, the chamfered VIA trench exposing at least a portion of the lower wiring line there below;
forming a monolayer upon the exposed portion of the lower wiring line within the VIA trench;
forming a dielectric film layer upon the vertical sidewall and the chamfered surface within the VIA trench and within the upper wiring line trench;
removing monolayer from the VIA trench to re-expose the portion of the lower wiring line while retaining the dielectric film layer upon the vertical sidewall and upon the chamfered surface within the VIA trench;
and
forming a chamfered VIA within the chamfered VIA trench at least upon the re-exposed portion of the lower wiring line.

4 more elements

Dependencies are inferred from the claim text.

Back end of line (beol) time dependent dielectric breakdown (tddb) mitigation within a vertical interconnect access (via) level of an integrated circuit (ic) device

Life of this patent

Back end of line (beol) time dependent dielectric breakdown (tddb) mitigation within a vertical interconnect access (via) level of an integrated circuit (ic) device

Life of this patent

Abstract

Claims15