US 2020/0395073 A1Published application

Ternary Content Addressable Memory Unit Capable Of Reducing Charge Sharing Effect

AssigneeUnited Microelectronics Corp.

InventorsChun-Yen Tseng, Ching-Cheng Lung, Yu-Tse Kuo, Chun-Hsien Huang, Chih-Wei Tsai, Hsin-Chih Yu, Shu-Ru Wang

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Abstract

A ternary content addressable memory unit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The first inverter includes an input terminal, and an output terminal coupled to a first node. The second inverter includes an input terminal coupled to the first node and an output terminal coupled to the input terminal of the first inverter. The third inverter includes an input terminal coupled to a second node and an output terminal. The fourth inverter includes an input terminal coupled to the output terminal of the third inverter and an output terminal coupled to the second node.

Claims18

Dependent claims

A ternary content addressable memory (TCAM) unit comprising:

a first inverter comprising:
an input terminal;
and
an output terminal coupled to a first node;
a second inverter comprising:
an input terminal coupled to the first node;
and
an output terminal coupled to the input terminal of the first inverter;
a third inverter comprising:
an input terminal coupled to a second node;
and
an output terminal;
a fourth inverter comprising:
an input terminal coupled to the output terminal of the third inverter;
and
an output terminal coupled to the second node;
a first transistor comprising:
a first terminal coupled to the first node;
a second terminal coupled to a first bitline;
and
a control terminal coupled to a first wordline;
a second transistor comprising:
a first terminal coupled to a second bitline;
a second terminal coupled to the input terminal of the first inverter;
and
a control terminal coupled to the first wordline;
a third transistor comprising:
a first terminal coupled to the second node;
a second terminal coupled to the first bitline;
and
a control terminal coupled to a second wordline;
a fourth transistor comprising:
a first terminal coupled to the second bitline;
a second terminal coupled to the output terminal of the third inverter;
and
a control terminal coupled to the second wordline;
a fifth transistor comprising:
a first terminal coupled to the first wordline;
a second terminal;
and
a control terminal coupled to a second searchline;
a sixth transistor comprising:
a first terminal coupled to the second terminal of the fifth transistor;
a second terminal coupled to a matchline;
and
a control terminal coupled to the first node;
a seventh transistor comprising:
a first terminal coupled to the matchline;
a second terminal;
and
a control terminal coupled to the second node;
and
an eighth transistor comprising:
a first terminal coupled to the second terminal of the seventh transistor;
a second terminal coupled to another first wordline;
and
a control terminal coupled to a first searchline;
wherein the first wordline and/or the second wordline is grounded;
and
the first wordline, the second wordline, and the matchline form a first metal layer of the TCAM unit.

57 more elements

A ternary content addressable memory (TCAM) unit comprising:

a first inverter comprising:
an input terminal;
and
an output terminal coupled to a first node;
a second inverter comprising:
an input terminal coupled to the first node;
and
an output terminal coupled to the input terminal of the first inverter;
a third inverter comprising:
an input terminal coupled to a second node;
and
an output terminal;
a fourth inverter comprising:
an input terminal coupled to the output terminal of the third inverter;
and
an output terminal coupled to the second node;
a first transistor comprising:
a first terminal coupled to the first node;
a second terminal coupled to a first bitline;
and
a control terminal coupled to a first wordline;
a second transistor comprising:
a first terminal coupled to a second bitline;
a second terminal coupled to the input terminal of the first inverter;
and
a control terminal coupled to the first wordline;
a third transistor comprising:
a first terminal coupled to the second node;
a second terminal coupled to the first bitline;
and
a control terminal coupled to a second wordline;
a fourth transistor comprising:
a first terminal coupled to the second bitline;
a second terminal coupled to the output terminal of the third inverter;
and
a control terminal coupled to the second wordline;
a fifth transistor comprising:
a first terminal coupled to the first wordline;
a second terminal;
and
a control terminal coupled to a second searchline;
a sixth transistor comprising:
a first terminal coupled to the second terminal of the fifth transistor;
a second terminal coupled to a matchline;
and
a control terminal coupled to the first node;
a seventh transistor comprising:
a first terminal coupled to the matchline;
a second terminal;
and
a control terminal coupled to the second node;
and
an eighth transistor comprising:
a first terminal coupled to the second terminal of the seventh transistor;
a second terminal coupled to another first wordline;
and
a control terminal coupled to a first searchline;
wherein the first wordline and/or the second wordline is floating;
and
the first wordline, the second wordline, and the matchline form a first metal layer of the TCAM unit.

57 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/503,617Filed 4 Jul 2019
Priority: TW 10812029212 Jun 2019
Published: 17 Dec 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 15/04
Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out…
H10B 10/12
Static random access memory [SRAM] devices: comprising a MOSFET load element
H10D 89/10
Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00: integrated device layouts
G11C
Static stores

Family

US 10,861,549 B1Related patent
US 2020/0395073 A1This patent

From the US filing history. Foreign family members aren’t listed.

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