Demultiplexer circuit, array substrate, display panel and device, and driveing method

An array substrate, comprising a substrate and a demultiplexer circuit disposed on the substrate, wherein the substrate comprises a display region and a non-display region adjacent to the display region, wherein the demultiplexer circuit is located in the non-display region;

• wherein the demultiplexer circuit comprises a plurality of demultiplexers, wherein each of the plurality of demultiplexers comprises at least two switching transistor groups, wherein each of the at least two switching transistor groups comprises at least two switching transistors;
• wherein sources of the at least two switching transistors in a same switching transistor group are electrically connected to each other to form a common source, and drains of the at least two switching transistors in the same switching transistor group are electrically connected to each other to form a common drain;
• and
• wherein each of the at least two switching transistor groups comprises one input end, one output end and at least two control ends;
• wherein input ends of the at least two switching transistor groups in a same demultiplexer are electrically connected to each other;
• wherein in the same switching transistor group, the common source is electrically connected to the input end, the common drain is electrically connected to the output end;
• and
• wherein the at least two control ends are electrically connected to gates of the at least two switching transistors in a one-to-one correspondence.

A display panel, comprising an array substrate, a plurality of data lines, and a plurality of subpixel units arranged in an array,

• wherein the array substrate comprises a substrate and a demultiplexer circuit disposed on the substrate, wherein the substrate comprises a display region and a non-display region adjacent to the display region, wherein the demultiplexer circuit is located in the non-display region, and wherein the demultiplexer circuit comprises a plurality of demultiplexers;
• wherein each of the plurality of demultiplexers comprises at least two switching transistor groups, wherein each of the at least two switching transistor groups comprises at least two switching transistors;
• wherein sources of the at least two switching transistors in a same switching transistor group are electrically connected to each other to form a common source, and drains of the at least two switching transistors in the same switching transistor group are electrically connected to each other to form a common drain;
• wherein each of the at least two switching transistor groups comprises one input end, one output end and at least two control ends, wherein input ends of the at least two switching transistor groups in a same demultiplexer are electrically connected to each other;
• wherein in a same switching transistor group, the common source is electrically connected to the input end, the common drain is electrically connected to the output end, and the at least two control ends are electrically connected to gates of the at least two switching transistors in a one-to-one correspondence;
• and
• wherein in the demultiplexer circuit on the array substrate, each switching transistor group in each demultiplexer is connected to a respective one of the plurality of data lines, and wherein each of the plurality of data lines is connected to a plurality of subpixel units in a same column.