Semiconductor memory devices having enhanced error correction circuits therein

A semiconductor memory device, comprising:

• a memory cell array including a plurality of bank arrays that respectively comprise a normal cell region, which stores main data, and a redundancy cell region, which stores first parity data associated with the corresponding main data;
• an error correction circuit configured to generate the parity data based on the main data using an error correction code (ECC), and to correct at least one error bit in the main data using the parity data, wherein the ECC is represented by a generation matrix;
• and
• a control logic circuit configured to control the error correction circuit based on a command and an address;
• wherein the main data includes a plurality of data bits divided into a plurality of sub data units;
• wherein the ECC includes a plurality of column vectors divided into a plurality of code groups corresponding to the sub data units;
• and
• wherein the column vectors have elements configured to gather a mis-corrected bit and multiple error bits in one symbol, wherein the mis-corrected bit is generated due to the multiple error bits in the main data.

A memory system, comprising:

• a semiconductor memory device;
• and
• a memory controller configured to control the semiconductor memory device;
• wherein the semiconductor memory device includes:
• a memory cell array including a plurality of bank arrays,
• wherein each of the plurality of bank arrays includes a normal cell region that stores main data, and a redundancy cell region that stores first parity data associated with the main data, and wherein each of the plurality of bank arrays includes a plurality of dynamic memory cells coupled to word-lines and bit-lines;
• an error correction circuit configured to generate the parity data based on the main data using a first error correction code (ECC), and to correct at least one error bit in the main data using the parity data, wherein the first ECC is represented by a generation matrix;
• and
• a control logic circuit configured to control the error correction circuit based on a command and an address provided from the memory controller;
• wherein the main data includes a plurality of data bits divided into a plurality of sub data units;
• wherein the first ECC includes a plurality of column vectors divided into a plurality of code groups corresponding to the sub data units, and
• wherein the column vectors have elements configured to gather a mis-corrected bit and multiple error bits in one symbol, wherein the mis-corrected bit is generated due to the multiple error bits in the main data.