Computational memory
AssigneeUntether Ai Corporation
InventorsWilliam Martin SNELGROVE, Darrick WIEBE
Life of this patent
Estimating the term…
Abstract
An example device includes a plurality of computational memory banks. Each computational memory bank of the plurality of computational memory banks includes an array of memory units and a plurality of processing elements connected to the array of memory units. The device further includes a plurality of single instruction, multiple data (SIMD) controllers. Each SIMD controller of the plurality of SIMD controllers is contained within at least one computational memory bank of the plurality of computational memory banks. Each SIMD controller is to provide instructions to the at least one computational memory bank.
Claims27
A device comprising:
- a plurality of computational memory banks, each computational memory bank of the plurality of computational memory banks including an array of memory units and a plurality of processing elements connected to the array of memory units;
- and
- a plurality of single instruction, multiple data (SIMD) controllers, each SIMD controller of the plurality of SIMD controllers being contained within at least one computational memory bank of the plurality of computational memory banks;
- wherein each SIMD controller is to provide instructions to the at least one computational memory bank;
- wherein each processing element of the plurality of processing elements includes static registers and an arithmetic logic unit (ALU) to perform operations with the static registers;
- and
- wherein each processing element of the plurality of processing elements is to receive communicated state from static registers of another processing element, the ALU to perform operations with the static registers and the communicated state.
(canceled)
(canceled)
A SIMD controller having instruction memory configured to be loaded from memory of one or more banks of computational memory, each bank of computational memory including the memory and a plurality of processing elements for performing parallel operations using the memory.
A plurality of SIMD controllers, each SIMD controller including instruction memory configured to be loaded from memory of one or more banks of computational memory, each bank of computational memory including the memory and a plurality of processing elements for performing parallel operations using the memory, wherein at least one of the SIMD controllers includes a decompressor operable to stream variable-length data from its instruction memory and produce decompressed information that includes one or both of fixed-length representations of coefficients and instructions, the plurality of SIMD controllers connected by a bus to share decompressed information.
A device comprising:
- a plurality of computational memory banks, each computational memory bank of the plurality of computational memory banks including an array of memory units and a plurality of processing elements connected to the array of memory units;
- and
- a plurality of single instruction, multiple data (SIMD) controllers, each SIMD controller of the plurality of SIMD controllers being contained within at least one computational memory bank of the plurality of computational memory banks;
- wherein each SIMD controller is to provide instructions to the at least one computational memory bank;
- and
- wherein each processing element of the plurality of processing elements includes static registers, and an arithmetic logic unit (ALU) to perform operations with the static registers, and communications registers that are slaved to the static registers, the communications registers to provide communicated state to another processing element.
A device comprising:
- a plurality of computational memory banks, each computational memory bank of the plurality of computational memory banks including an array of memory units and a plurality of processing elements connected to the array of memory units;
- a plurality of single instruction, multiple data (SIMD) controllers, each SIMD controller of the plurality of SIMD controllers being contained within at least one computational memory bank of the plurality of computational memory banks, wherein each SIMD controller is to provide instructions to the at least one computational memory bank;
- and
- a bus connecting processing elements of a computational memory bank of the plurality of computational memory banks to processing elements of another computational memory bank of the plurality of computational memory banks.
A device comprising:
- a plurality of computational memory banks, each computational memory bank of the plurality of computational memory banks including an array of memory units and a plurality of processing elements connected to the array of memory units;
- a plurality of single instruction, multiple data (SIMD) controllers, each SIMD controller of the plurality of SIMD controllers being contained within at least one computational memory bank of the plurality of computational memory banks, wherein each SIMD controller is to provide instructions to the at least one computational memory bank;
- and
- a plurality of busses, each bus operable to unidirectionally or bidirectionally communicate information among any of the computational memory banks, wherein at least one of the busses is segmented and at least another of the busses is not segmented.
A device comprising:
- a plurality of computational memory banks, each computational memory bank of the plurality of computational memory banks including an array of memory units and a plurality of processing elements connected to the array of memory units;
- a plurality of single instruction, multiple data (SIMD) controllers, each SIMD controller of the plurality of SIMD controllers being contained within at least one computational memory bank of the plurality of computational memory banks, wherein each SIMD controller is to provide instructions to the at least one computational memory bank;
- and
- a bus connecting the plurality of SIMD controllers.
Dependencies are inferred from the claim text.