Limiting replay of load-based control independent (ci) instructions in speculative misprediction recovery in a processor

A method of designating load-based control independent (CI) instructions in an instruction stream in a processor as load-based CI, data dependent (DD) (CIDD) instructions for replay in misprediction recovery, comprising:

• fetching a plurality of instructions from a memory into an instruction pipeline among the one or more instruction pipelines, the plurality of fetched instructions in the one or more instruction pipelines comprising an instruction stream comprising at least one control independent (CI) instruction region and a plurality of control dependent (CD) instruction regions;
• speculatively predicting a predicate in a conditional control instruction in the instruction stream;
• processing fetched instructions in the instruction stream comprising fetched instructions in a first CD instruction region among the plurality of CD instruction regions in the instruction stream taken based on the speculative prediction and a load-based CI instruction in a CI instruction region;
• determining if the load-based CI instruction is a store-forward dependent (SFD) load-based CI instruction based on determining if a store-based instruction in the instruction stream designates a forward store for consumption by the load-based CI instruction;
• executing the conditional control instruction to resolve the predicate of the conditional control instruction;
• determining if the speculative prediction matches the resolved predicate from execution of the conditional control instruction;
• and
• in response to the speculative prediction not matching the resolved predicate in execution of the conditional control instruction:
• processing the fetched instructions in a second CD instruction region among the plurality of CD instruction regions in the instruction stream taken based on the resolved predicate from execution of the conditional control instruction and the load-based CI instruction;
• and
• replaying the processed load-based CI instruction in response to determining the load-based CI instruction is a SFD load-based CI instruction.

A processor, comprising:

• an instruction processing circuit comprising one or more instruction pipelines;
• the instruction processing circuit configured to:
• fetch a plurality of instructions from a memory into an instruction pipeline among the one or more instruction pipelines, the plurality of fetched instructions in the one or more instruction pipelines comprising an instruction stream comprising at least one control independent (CI) instruction region and a plurality of control dependent (CD) instruction regions;
• speculatively predict a predicate in a conditional control instruction in the instruction stream;
• process fetched instructions in the instruction stream comprising fetched instructions in a first CD instruction region among the plurality of CD instruction regions in the instruction stream taken based on the speculative prediction and a load-based CI instruction in a CI instruction region;
• determine if the load-based CI instruction is predicted to have a memory dependence on a store-based instruction in the instruction stream;
• execute the conditional control instruction to resolve the predicate of the conditional control instruction;
• determine if the speculative prediction matches the resolved predicate from execution of the conditional control instruction;
• and
• in response to the speculative prediction not matching the resolved predicate in execution of the conditional control instruction:
• process the fetched instructions in a second CD instruction region among the plurality of CD instruction regions in the instruction stream taken based on the resolved predicate from execution of the conditional control instruction and the load-based CI instruction;
• determine if the load-based CI instruction had the predicted memory dependence as a store-forward dependent (SFD) load-based CI instruction;
• and
• in response to determining the load-based CI instruction had the predicted memory dependence as the SFD load-based CI instruction, replay the executed load-based CI instruction as a load-based CI, data dependent (DD) (CIDD) instruction.