FinFET Device and Method of Manufacture

A device comprising:

• a semiconductor fin protruding from a substrate;
• an isolation region surrounding the semiconductor fin;
• a gate stack over the semiconductor fin;
• a spacer layer on sidewalls of the gate stack;
• a source/drain region on the semiconductor fin adjacent the gate stack;
• a low-k dielectric layer on the top and sidewalls of the source/drain region and on the spacer layer, wherein the low-k dielectric layer has a lower dielectric constant than the spacer layer;
• an etch stop layer on the low-k dielectric layer, wherein the etch stop layer is a different material than the low-k dielectric layer;
• and
• a source/drain contact extending through the etch stop layer and the low-k dielectric layer to contact the source/drain region.

A device comprising:

• a plurality of fins over a semiconductor substrate;
• a gate structure on upper surfaces and sidewalls of the plurality of fins;
• gate spacers along sidewalls of the gate structure;
• fin spacers on sidewalls of each fin of the plurality of fins;
• an epitaxial source/drain region on the plurality of fins adjacent the gate structure, wherein the epitaxial source/drain region has a first sidewall and a second sidewall opposite the first sidewall, wherein the first sidewall is adjacent a first fin of the plurality of fins, and wherein the second sidewall is adjacent a second fin of the plurality of fins;
• a capping layer extending conformally on the first sidewall of the epitaxial source/drain region, on the second sidewall of the epitaxial source/drain region, on a top surface of the epitaxial source/drain region, on the gate spacers, on a first fin spacer on a sidewall of the first fin, and on a second fin spacer on a sidewall of the second fin, wherein the capping layer on the top surface of the epitaxial source/drain region has a smaller thickness than the capping layer on the first fin spacer and the second fin spacer;
• and
• an etch stop layer on the capping layer.