Integrated circuit layout method, device, and system
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChien-Ying CHEN, Lee-Chung LU, Li-Chun TIEN, Ta-Pen GUO
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChien-Ying CHEN, Lee-Chung LU, Li-Chun TIEN, Ta-Pen GUO
Estimating the term…
A method of generating a layout diagram of an IC cell includes defining a boundary recess in a boundary of the cell by extending a first portion of the boundary along a first gate track, extending a second portion of the boundary from the first gate track to a second gate track, the second portion being contiguous with the first portion, and extending a third portion of the boundary from the first gate track to the second gate track, the third portion being contiguous with the first portion An active region is positioned in the cell by extending the active region across a third gate track, wherein the first gate track is between the second gate track and the third gate track. The layout diagram is stored on a non-transitory computer-readable medium.
A method of generating a layout diagram of an integrated circuit (IC) cell, the IC layout diagram being stored on a non-transitory computer-readable medium, the method comprising:
An integrated circuit (IC) device comprising:
An electronic design automation (EDA) system comprising:
Dependencies are inferred from the claim text.