Stacked transistors with different channel widths

A semiconductor integrated circuit comprising:

• a first stack of nanowires above a substrate;
• a first gate structure over, around, and between the first stack of nanowires;
• a second stack of nanowires above the substrate;
• a second gate structure over, around, and between the second stack of nanowires;
• a first source/drain region contacting a first number of nanowires of the first nanowire stack;
• and
• a second source/drain region contacting a second number of nanowires of the second nanowire stack;
• wherein the first number and second number of contacted nanowires are different, and
• wherein the number of nanowires in the first and second nanowire stacks is the same.