Poly gate extension design methodology to improve cmos performance in dual stress liner process flow
AssigneeTexas Instruments Incorporated
InventorsYounsung Choi, Steven Lee Prins
Life of this patent
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Abstract
An integrated circuit and method with dual stress liners and with NMOS transistors with gate overhang of active that is longer than the minimum design rule and with PMOS transistors with gate overhang of active that are not longer than the minimum design rule.
Claims18
A method of forming an integrated circuit having a first and an adjacent second NMOS transistor and a first and an adjacent second PMOS transistor, comprising:
- forming a first NMOS gate of the first NMOS transistor and a second NMOS gate of the second NMOS transistor, wherein the first NMOS transistor has a first width smaller than a second width of the second NMOS transistor and the first NMOS gate and second NMOS gate have a same long side dimension;
- forming a first PMOS gate of the first PMOS transistor and a second PMOS gate of the second PMOS transistor, wherein the first PMOS transistor has a third width smaller than a fourth width of the second PMOS transistor and wherein forming the first PMOS gate forms an additional extension with a gap between a first edge of the extension and the first PMOS gate and a second opposite edge aligned with an edge of the second PMOS gate.
A method of forming an integrated circuit having a first and an adjacent second NMOS transistor and a first and an adjacent second PMOS transistor, comprising:
- forming a first NMOS gate of the first NMOS transistor and a second NMOS gate of the second NMOS transistor, wherein forming the first NMOS gate forms a first optical proximity correction (OPC) extension continuous with the first NMOS gate;
- forming a first PMOS gate of the first PMOS transistor and a second PMOS gate of the second PMOS transistor, wherein the first PMOS transistor has a third width smaller than a fourth width of the second PMOS transistor and wherein forming the first PMOS gate forms a second OPC extension with a gap between a first edge of the second OPC extension and the first PMOS gate.
An integrated circuit having a first and an adjacent second NMOS transistor and a first and an adjacent second PMOS transistor, comprising:
- a first NMOS gate of the first NMOS transistor and a second NMOS gate of the second NMOS transistor, wherein the first NMOS transistor has a first width smaller than a second width of the second NMOS transistor;
- a first optical proximity correction (OPC) extension continuous with the first NMOS gate;
- a first PMOS gate of the first PMOS transistor and a second PMOS gate of the second PMOS transistor, wherein the first PMOS transistor has a third width smaller than a fourth width of the second PMOS transistor;
- and
- a second OPC extension with a gap between a first edge of the second OPC extension and the first PMOS gate and a second opposite edge aligned with an edge of the second PMOS gate.
An integrated circuit having a first and an adjacent second NMOS transistor and a first and an adjacent second PMOS transistor, comprising:
- a first NMOS gate of the first NMOS transistor and a second NMOS gate of the second NMOS transistor, wherein the first NMOS transistor has a first width smaller than a second width of the second NMOS transistor and the first NMOS gate has a NMOS extension continuous with the first NMOS gate such that the first NMOS gate and the NMOS extension together have a same long side dimension as the second NMOS gate;
- a first PMOS gate of the first PMOS transistor and a second PMOS gate of the second PMOS transistor, wherein the first PMOS transistor has a third width smaller than a fourth width of the second PMOS transistor;
- and
- a PMOS extension for the first PMOS gate with a gap between a first edge of the PMOS extension and the first PMOS gate and a second opposite edge aligned with an edge of the second PMOS gate.
Dependencies are inferred from the claim text.