Memory system capable of reducing the reading time

A memory system comprising:

• a plurality of first memory cells coupled to a first bit line;
• a voltage bias transistor having a first terminal configured to receive a first system voltage, a second terminal, and a control terminal;
• a first page buffer coupled to the first bit line and the second terminal of the voltage bias transistor;
• a common source transistor having a first terminal coupled to the first bit line, a second terminal configured to receive a second system voltage, and a control terminal;
• and
• a bias circuit comprising:
• a charging current reproduce unit coupled to the voltage bias transistor, and configured to generate a charging reference voltage according to a charging current flowing through the voltage bias transistor;
• a cell current reproduce unit coupled to the common source transistor, and configured to generate a cell reference voltage according to a cell current flowing through the common source transistor;
• a current comparator coupled to the charging current reproduce unit and the cell current reproduce unit, and comprising:
• a first current generator configured to generate a first replica charging current according to the charging reference voltage;
• and
• a second current generator configured to generate a first replica cell current according to the cell reference voltage;
• and
• a bit line bias generator coupled to the current comparator and the first page buffer, and configured to generate the bit line bias voltage according to a difference between the first replica charging current and the first replica cell current.