Peak current management in a memory array

A method of operating a memory device comprising multiple memory dice, the method comprising:

• performing one or more memory events using a first memory die of the multiple memory dice using a high current mode, wherein the memory events can be performed in the high current mode using a high current level or in a low current mode using a lower current level;
• indicating by a common power status interface common to the multiple memory dice when the first memory die is operating in the high current mode and the high current mode is unavailable to other memory dice of the multiple memory dice, and indicating by the common power status interface when the high current mode is unused by the first memory die and the high current mode is available to the other memory dice;
• operating, in response to polling the power status interface, a second memory die to execute the one or more memory events in the high current mode using a high current level when the polling indicates the high current mode is available to the second memory the;
• and
• operating the second memory die to execute the same one or more memory events in a low current mode using a lower current level when the polling indicates the high current mode is unavailable to the second memory die.

A memory device comprising multiple memory dice, wherein each memory die of the multiple memory die includes:

• a memory array including memory cells;
• charging circuitry configured to perform one or more memory events in a high current mode using a high current level or in a low current mode using a lower current level;
• a high current mode input-output (I/O) pad operatively coupled to a high current mode I/O pad of the other memory dice;
• a memory control unit operatively coupled to the memory array, the charging circuitry, and the high current mode I/O pad, and configured to:
• poll the high current mode I/O pad to determine when the high current mode is available and unused by the other memory dice;
• operate the charging circuitry in the high current mode to perform the one or more memory events when the high current mode is available, and indicate use of the high current mode using the high current mode I/O pad;
• and
• operate the charging circuitry in the low current mode to perform the one or more memory events when the high current mode is unavailable.

A multi-chip package comprising:

• multiple memory dice that include:
• a memory array;
• a power status interface shared between the multiple memory dice, the shared power status interface configured to provide an indication of available power to a memory die;
• and
• a control unit in communication with the power status interface, the control unit configured to:
• receive requests for memory events for at least a portion of the memory array of the memory die;
• for requested memory events that can be performed in either a high current mode using a high current level or in a low current mode using a lower current level, poll the shared power status interface to identify available power for the requested memory event;
• perform a first requested memory event in the high current mode when the shared power status interface indicates that the high current mode is available and unused by another memory die;
• and
• perform a second requested memory event in the low current mode when the shared power status interface indicates that the high current mode is unavailable and in use by the other memory die.

An electronic system, comprising:

• multiple memory dice that include:
• a memory array;
• a power status interface shared between the multiple memory dice, the shared power status interface configured to provide an indication of available power to a memory die;
• and
• a control unit in communication with the power status interface, the control unit configured to:
• receive requests for memory events for at least a portion of the memory array of the memory die;
• for requested memory events that can be performed in either a high current mode or in a low current mode, poll the shared power status interface to identify available power for the requested memory event;
• perform a first requested memory event in a high current mode when the shared power status interface indicates that the high current mode is available and unused by another memory die;
• and
• perform a second requested memory event in a low current mode when the shared power status interface indicates that the high current mode is unavailable and in use by the other memory die.