US 2020/0350016 A1 · SEMICONDUCTOR MEMORY DEVICE

Abstract

A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

Claims13

Dependent claims

A semiconductor memory device comprising:

a substrate;
first and second P-type well regions on the substrate;
an N-type well region on the substrate and sandwiched between the first P-type well region and a second P-type well region;
a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring;
and
a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

3 more elements

A semiconductor memory device comprising:

a first power supply protection circuit and a second power supply protection circuit;
and
a pad supplied with a first voltage from an outside, and electrically connected to a first node, wherein
the first power supply protection circuit includes:
a first resistance including a first end electrically connected to the first node and a second end electrically connected to a second node;
and
a first transistor configured to supply a second voltage different from the first voltage to the second node, and
the second power supply protection circuit includes:
a second resistance including a first end electrically connected to the first node and a second end electrically connected to a third node;
and
a second transistor configured to supply the second voltage to the third node.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/934,978Filed 21 Jul 2020

Priority

JP 2018-0901518 May 2018

Published

5 Nov 2020

Term ends

Not estimatedThe source records don’t support an estimate.

Classification15 codes

G11C 5/147
Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels: voltage…
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 7/109
Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits: control signal input…
G11C 7/24
Arrangements for writing information into, or reading information out from, a digital store: memory cell safety or protection circuits, e.g.…

Semiconductor memory device

Life of this patent

Semiconductor memory device

Life of this patent

Abstract

Claims13