Cache coherency management for multi-category memories
AssigneeHewlett Packard Enterprise Development LP
InventorsFrank R. Dropps, Michael S. Woodacre, Thomas McGee, Michael Malewicki
Life of this patent
Estimating the term…
Loading patent…
AssigneeHewlett Packard Enterprise Development LP
InventorsFrank R. Dropps, Michael S. Woodacre, Thomas McGee, Michael Malewicki
Estimating the term…
In exemplary aspects of cache coherency management, a first request is received and includes an address of a first memory block in a shared memory. The shared memory includes memory blocks of memory devices associated with respective processors. Each of the memory blocks are associated with one of a plurality of memory categories indicating a protocol for managing cache coherency for the respective memory block. A memory category associated with the first memory block is determined and a response to the first request is based on the memory category of the first memory block. The first memory block and a second memory block are included in one of the same memory devices, and the memory category of the first memory block is different than the memory category of the second memory block.
An apparatus comprising:
A method comprising:
A system, comprising:
The system of claim 20, wherein the first request is originated from a processor and transmitted to the first node controller by a second node controller associated with the processor.
Dependencies are inferred from the claim text.