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US 2020/0348939 A1Published application
Hardware processors and methods for extended microcode patching
AssigneeIntel Corporation
InventorSergiu D. Ghetie
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AssigneeIntel Corporation
InventorSergiu D. Ghetie
Estimating the term…
Hardware processors and methods for extended microcode patching through on-die and off-die secure storage are described. In one embodiment, the additional storage resources used for storing micro-operations are section(s) of a cache that are unused at runtime and/or unused by a configuration of a processor. For example, the additional storage resources may be a section of a cache that is used to store context information from a core when the core is transitioned to a power state that shuts off voltage to the core. Non-limiting examples of such sections are one or more sections for storage of context information for a transition of a thread to idle or off, storage of context information for a transition of a core for a multiple core processor to idle or off, or storage of coherency information for a transition of a cache coherency circuit (e.g., cache box (CBo)) to idle or off.
A processor comprising:
A method comprising:
A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:
Dependencies are inferred from the claim text.