Computation Engine that Operates in Matrix and Vector Modes

A computation engine configured to execute a compute instruction, the computation engine comprising:

• a circuit configured to perform a multiplication operation on a first operand and a second operand responsive to a vector/matrix mode selection coded into the compute instruction indicating a matrix mode, producing a result matrix, and the circuit configured to perform a vector multiplication operation on the first operand and the second operand responsive to the vector/matrix mode selection indicating a vector mode, producing a result vector;
• a first memory coupled to the circuit, wherein the first memory is configured to store the first operand;
• a second memory coupled to the circuit, wherein the second memory is configured to store the second operand;
• and
• a third memory coupled to the circuit, wherein the third memory is configured to store result vector or the result matrix from the circuit, wherein the third memory comprises a plurality of entries, and wherein the circuit is configured to write the result vector to a single entry of the plurality of entries, and wherein the circuit is configured to write the result matrix to a plurality of the plurality of entries, wherein the plurality of the plurality of entries includes the single entry, and wherein computation engine is configured to generate results having a plurality of sizes, and wherein the computation engine is configured to include space between the plurality of entries when the result matrix has a size less than a largest size of the plurality of sizes.