Error scaling in crest factor reduction

A crest factor reduction, CFR, circuit configured to regulate a peak to average power ratio, PAR, of an output signal of the CFR circuit the circuit comprising:

• a magnitude determiner configured to determine a magnitude of an input signal;
• a clipping circuit configured to clip the input signal to a target level to produce an error signal by comparing the input signal magnitude to a threshold and capturing a portion of the magnitude exceeding the threshold;
• a filter configured to filter the error signal to produce a processed error signal, the filtering providing a band pass filter frequency response;
• a gain circuit configured to scale the processed error signal by an error scaling factor to achieve a target signal to noise ratio, SNR, for the output signal based on a target error vector magnitude, EVM, the scaling functioning to regulate the output signal of the CFR circuit.

An error scaling circuit, comprising:

• an input signal level determiner configured to determine a level of a input signal power;
• a processed error signal level determiner configured to determine a level of a processed error signal power, the first processed error signal being obtained from a signal clipped to a target level;
• a signal to noise ratio, SNR, memory configured to store an SNR level, the SNR level being based on a target error vector magnitude, EVM;
• and
• an error scaling factor calculator configured to calculate an error scaling factor to scale the first processed error signal to achieve the SNR level.