Low power logic family

A semiconductor building block, comprising:

• a plurality of logic gates, each having
• at least one P-channel device,
• at least one N-channel device, and
• a current controller controlling current for each of the plurality of logic gate, having
• a voltage source input (vdd),
• a ground input (vss),
• a first input current (ibiasn) adapted to control current through the at least one N-channel device,
• a second input current (ibiasp) adapted to control current through the at least one P-channel device, and
• an analog voltage input (delta) representing i) a predetermined ratio between respective on currents in the at least one P-channel device to ibiasp, and ii) the predetermined ratio between respective on currents in the at least one N-channel device to ibiasn, wherein the on-current through the at least one P-channel device and the on-current through the at least one N-channel device are substantially equal and are controlled by a current control circuit, and
• wherein the current control circuit is adapted to utilize ibiasp, ibiasnand delta to generate i) a controlled supply voltage (vsp) for the at least one P-channel device, and ii) a controlled body voltage (vtub) for the at least one P-channel device.