On-die termination control
AssigneeRambus Inc.
InventorsKyung Suk Oh, Ian P. Shaeffer
Life of this patent
Estimating the term…
Abstract
A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs.
Claims21
1-20. (canceled)
An integrated circuit device comprising:
- a first signaling interface to be coupled to a dynamic random access memory component (DRAM), the DRAM having a first register to store a first control value and a second register to store a second control value;
- and
- control circuitry to transmit to the DRAM via the first signaling interface one or more commands that instruct the DRAM to:
- store the first control value within the first register of the DRAM, the first control value specifying a first termination to be applied to a data interface of the DRAM during a write-data reception interval in which write data is received by the DRAM via the data interface;
- and
- store the second control value within the second register of the DRAM, the second control value specifying a second termination that is to be applied to the data interface after the write-data reception interval transpires.
The integrated circuit device of 24 further comprising a second signaling interface comprising a plurality of command/address signal receivers to receive commands from a memory controller and a plurality of data signal transceivers to output data signals to and receive data signals from the memory controller.
A method of operation within an integrated circuit device, the method comprising:
- transmitting, to a dynamic random access memory component (DRAM) via a first signaling interface, one or more commands that instruct the DRAM to:
- store a first control value within a first register of the DRAM, the first control value specifying a first termination to be applied to a data interface of the DRAM during a write-data reception interval in which write data is received by the DRAM via the data interface;
- and
- store a second control value within a second register of the DRAM, the second control value specifying a second termination that is to be applied to the data interface after the write-data reception interval transpires;
- and
- transmitting to the DRAM via the first signaling interface a write command indicating that the write data is to be received within the DRAM component.
The method of 34 further receiving commands from a memory controller via a second signaling interface and outputting data signals to and receiving data signals from the memory controller via the second signaling interface.
An integrated circuit device comprising:
- a first signaling interface to be coupled to a dynamic random access memory component (DRAM);
- and
- means for transmitting to the DRAM via the first signaling interface one or more commands that instruct the DRAM to:
- store a first control value within a first register of the DRAM, the first control value specifying a first termination to be applied to a data interface of the DRAM during a write-data reception interval in which write data is received by the DRAM via the data interface;
- and
- store a second control value within a second register of the DRAM, the second control value specifying a second termination that is to be applied to the data interface after the write-data reception interval transpires.
Dependencies are inferred from the claim text.