Input/output circuit and method

A circuit comprising:

• a first power node configured to carry a first voltage having a first voltage level;
• a second power node configured to carry a second voltage having a second voltage level;
• a third power node configured to carry a third voltage having a third voltage level;
• a fourth power node configured to carry a fourth voltage having a zero reference level;
• an output node;
• first and second cascode transistors coupled between the first power node and the output node and to each other at a first node;
• third and fourth cascode transistors coupled between the output node and the fourth power node and to each other at a second node;
• a bias circuit configured to use the first through fourth cascode transistors to generate an output signal at the output node that transitions between the first voltage level and the zero reference level;
• a first delay circuit configured to generate a falling edge in a first signal from the first voltage level to the second voltage level, the falling edge having a first time delay based on the output signal;
• a first contending transistor configured to, responsive to the first signal, couple the first node to the second power node;
• a second delay circuit configured to generate a rising edge in a second signal from the zero reference level to the third voltage level, the rising edge having a second time delay based on the output signal;
• and
• a second contending transistor configured to, responsive to the second signal, couple the second node to the third power node.

A method comprising:

• using a bias circuit to control first and second cascode transistors coupled between a first power node and an output node of a circuit, thereby generating an output signal at the output node, the output signal ranging between a first voltage level carried on the first power node and a second voltage level;
• using a contending transistor to selectively couple a node between the first and second cascode transistors to a second power node carrying a third voltage level;
• and
• based on the output signal, using a delay circuit to adjust a time delay of a transition in a first signal from one of the first or third voltage levels to the other of the first or third voltage levels,
• wherein the selective coupling of the contending transistor is based on the adjusted time delay.