Wrap Around Silicide for FinFETs
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuo-Cheng Chiang, Chi-Wen Liu, Ying-Keung Leung
Life of this patent
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Abstract
A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.
Claims20
A device comprising:
- a semiconductor substrate;
- isolation regions extending into the semiconductor substrate;
- a semiconductor fin between opposing portions of the isolation regions and protruding higher than the isolation regions;
- a gate stack on a first sidewall and a first top surface of the semiconductor fin;
- a source/drain region on a side of, and connecting to, the semiconductor fin;
- and
- a silicide region contacting a second top surface and second sidewalls of the source/drain region, wherein the silicide region extends to top surfaces of the isolation regions.
A device comprising:
- a first isolation region;
- a second isolation region;
- a semiconductor strip comprising:
- a first sidewall contacting the first isolation region;
- and
- a second sidewall contacting the second isolation region, wherein the first sidewall and the second sidewall have a first lateral distance;
- and
- a semiconductor fin overlapping the semiconductor strip, wherein the semiconductor fin is higher than top surfaces of the first isolation region and the second isolation region;
- a gate stack on the semiconductor fin;
- a source/drain region connected to the semiconductor fin, wherein the source/drain region overlaps the semiconductor strip, and the source/drain region comprises a third sidewall and a fourth sidewall opposite to each other, and wherein the third sidewall and the fourth sidewall have a second lateral distance greater than the first lateral distance;
- and
- a silicide region contacting both of the third sidewall and the fourth sidewall of the source/drain region.
A device comprising:
- a semiconductor substrate;
- isolation regions extending into the semiconductor substrate;
- a semiconductor fin higher than the isolation regions;
- a gate stack on the semiconductor fin;
- a source/drain region on a side of and connecting to the semiconductor fin;
- and
- a silicide region contacting opposing sidewalls and a top surface of the source/drain region, wherein the silicide region extends from a top surface of the source/drain region to the isolation regions.
Dependencies are inferred from the claim text.