Forming Gate Last Vertical FET With Self-Aligned Spacers and Junctions

A method of forming a VFET device, the method comprising the steps of:

• forming a stack on a wafer, the stack comprising:
• i) a doped bottom source and drain disposed on the wafer, ii) sacrificial layers disposed on the bottom source and drain, comprising layers of a first sacrificial material with a layer of a second sacrificial material therebetween, and iii) a doped top source and drain disposed on the sacrificial layers, wherein the first sacrificial material comprises SiGe having a Ge content of from about 60% Ge to about 100% Ge and ranges therebetween, and wherein the second sacrificial material comprises SiGe having a Ge content of from about 30% Ge to about 60% Ge and ranges therebetween;
• patterning trenches in the stack to form individual gate regions;
• filling the trenches with a channel material between the gate regions to form vertical fin channels, wherein the channel material comprises epitaxial Si;
• selectively removing the layers of the first sacrificial material from the stack forming first cavities in the gate regions;
• forming gate spacers in the first cavities;
• selectively removing the layer of the second sacrificial material from the stack forming second cavities in the gate regions;
• annealing the stack to diffuse dopants from the doped bottom source and drain and the doped top source and drain into the channel material between adjacent gate regions, forming bottom source and drain extensions and top source and drain extensions;
• and
• forming replacement metal gates in the second cavities.

A VFET device, comprising:

• a wafer;
• gate regions on the wafer, the gate regions each comprising:
• i) a doped bottom source and drain disposed on the wafer, ii) a replacement metal gate above the doped bottom source and drain, iii) a doped top source and drain above the replacement metal gate, and iv) gate spacers offsetting the replacement metal gate from the doped bottom source and drain, and from the top doped source and drain;
• vertical fin channels between the gate regions;
• and
• bottom source and drain extensions and top source and drain extensions between adjacent gate regions.