Single transistor with strained and de-polarizing anti-ferroelectric and ferroelectric oxide

A field effect transistor (FET) comprising:

• a substrate;
• a source and drain adjacent to the substrate;
• a semiconductor body between the source and drain;
• a gate stack between the source and drain, wherein the gate stack includes:
• a first structure comprising a high K dielectric;
• a second structure comprising strained ferroelectric (FE) material or strained anti-FE material, wherein the second structure is adjacent to the first structure;
• and
• a third structure comprising metal;
• and
• first and second spacers on either side of the gate stack and adjacent to the gate stack, wherein the first spacer is adjacent to the source, and wherein the second spacer is adjacent to the drain.

A system comprising:

• a memory;
• a processor coupled to the memory, the processor including a transistor having a gate stack comprising:
• a first structure comprising a semiconductor material;
• a second structure comprising a depolarized ferroelectric (FE) material or depolarized anti-FE material;
• wherein the second structure is over the first structure;
• a third structure comprising FE material or an anti-FE material, wherein the third structure is over the second structure;
• and
• a fourth structure comprising metal, wherein the fourth structure is adjacent to the third structure;
• and
• a wireless interface to allow the processor to communicate with another device.