US 2020/0287003 A1 · Integrated Assemblies Having Polycrystalline First Semiconductor Material Adjacent Conductively-Doped Second Semiconductor Material

Abstract

Some embodiments include an integrated assembly having a polycrystalline first semiconductor material, and having a second semiconductor material directly adjacent to the polycrystalline first semiconductor material. The second semiconductor material is of a different composition than the polycrystalline first semiconductor material. A conductivity-enhancing dopant is within the second semiconductor material. The conductivity-enhancing dopant is a neutral-type dopant relative to the polycrystalline first semiconductor material. An electrical gate is adjacent to a region of the polycrystalline first semiconductor material and is configured to induce an electric field within said region of the polycrystalline first semiconductor material. The gate is not adjacent to the second semiconductor material.

Claims37

Dependent claims

An integrated assembly, comprising:

a polycrystalline first semiconductor material;
a second semiconductor material directly adjacent to the polycrystalline first semiconductor material and being of a different composition than the polycrystalline first semiconductor material;
a conductivity-enhancing dopant within the second semiconductor material, the conductivity-enhancing dopant being a neutral-type dopant relative to the polycrystalline first semiconductor material;
and
an electrical gate adjacent to a region of the polycrystalline first semiconductor material and being configured to induce an electric field within said region of the polycrystalline first semiconductor material;
the gate not being adjacent to the second semiconductor material.

3 more elements

An integrated assembly, comprising:

a base;
a vertically extending pillar of polycrystalline semiconductor material supported by the base;
the pillar having a bottom side and a top side;
the pillar comprising a channel region between the bottom and top sides;
a first source/drain material under the pillar and adjacent to the bottom side;
a first conductivity-enhancing dopant within the first source/drain material, the first conductivity-enhancing dopant being a neutral-type dopant relative to the polycrystalline semiconductor material;
a second source/drain material over the pillar and adjacent to the top side;
a second conductivity-enhancing dopant within the second source/drain material, the second conductivity-enhancing dopant being a neutral-type dopant relative to the polycrystalline semiconductor material;
a transistor gate adjacent to the polycrystalline semiconductor material and not being adjacent to the first and second source/drain materials, and being configured to gatedly couple the first and second source/drain materials through the channel region;
and
a charge-storage device coupled with one of the first and second source/drain materials.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/294,759Filed 6 Mar 2019

Published

10 Sep 2020

Term ends

Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10D 30/6728
Thin-film transistors [TFT]: vertical TFTs
H10D 62/82
Characterised by the materials: heterojunctions
H10B 12/30
Dynamic random access memory [DRAM] devices: dRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
H10B 12/31
DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells: having a storage electrode stacked over the transistor

Integrated Assemblies Having Polycrystalline First Semiconductor Material Adjacent Conductively-Doped Second Semiconductor Material

Life of this patent

Integrated Assemblies Having Polycrystalline First Semiconductor Material Adjacent Conductively-Doped Second Semiconductor Material

Life of this patent

Abstract

Claims37