High-performance lateral bjt with epitaxial lightly doped intrinsic base
AssigneeInternational Business Machines Corporation
InventorsPouya Hashemi, Tak H. Ning, Jeng-Bang Yau
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Abstract
High-performance lateral bipolar junction transistors (BJTs) are provided in which a lightly doped upper intrinsic base region is formed between a lower intrinsic base region and an extrinsic base region. The lightly doped upper intrinsic base region provides two electron paths which contribute to the collector current, IC. The presence of the lightly doped upper intrinsic base region increases the total IC and leads to higher current gain, β, if there is no increase of the base current, IB.
Claims20
A lateral bipolar junction transistor (BJT) comprising:
- a lower intrinsic base region composed of a first semiconductor material of a first conductivity type located on a surface of a layer that is composed of at least a partially insulating material;
- an upper intrinsic base region composed of a second semiconductor material of the first conductivity type located on the lower intrinsic base region, wherein the upper intrinsic base region has a lower dopant concentration than the lower intrinsic base region;
- an extrinsic base region composed of a third semiconductor material of the first conductivity type located on the upper intrinsic base region, wherein the extrinsic base region has a higher dopant concentration than both the upper and lower intrinsic base regions;
- an emitter region composed of a fourth semiconductor material of a second conductivity type, opposite the first conductivity type, located laterally adjacent to, and contacting, a first side of the lower intrinsic base region;
- and
- a collector region composed of the fourth semiconductor material of the second conductivity located laterally adjacent to, and contacting, a second side of the lower intrinsic base region, which is opposite the first side of the lower intrinsic base region.
A method of forming a lateral bipolar junction transistor (BJT), the method comprising:
- forming an upper intrinsic base layer composed of a second semiconductor material of a first conductivity type on a surface of a lower intrinsic base layer composed of a first semiconductor material of the first conductivity type, wherein the lower intrinsic base layer is present on a surface of a layer that is composed of at least a partially insulating material;
- a first patterned material stack on a surface of the upper intrinsic base layer, wherein the first patterned material stack includes at least an extrinsic base region composed of a third semiconductor material of the first conductivity type;
- patterning the upper intrinsic base layer to provide a second patterned material stack utilizing the first patterned material stack as an etch mask, wherein the second patterned material stack includes at least a remaining portion of the upper intrinsic base layer which defines an upper intrinsic base region, and the extrinsic base region;
- forming a dielectric spacer along a sidewall of the second patterned material stack and in both an emitter-side and a collector-side of the second patterned material stack;
- creating a notch into the lower intrinsic base layer that is located on both the emitter-side and the collector-side to provide a faceted intrinsic base portion in both the emitter-side and the collector-side;
- and
- forming an emitter region composed of a fourth semiconductor material of a second conductivity type that is opposite the first conductivity type in the emitter-side and a collector region composed of the fourth semiconductor material of the second conductivity type in the collector-side.
Dependencies are inferred from the claim text.