US 2020/0286992 A1 · SOURCE/DRAIN EXTENSION REGIONS AND AIR SPACERS FOR NANOSHEET FIELD-EFFECT TRANSISTOR STRUCTURES

Abstract

A method of forming a semiconductor structure includes forming a nanosheet stack over a substrate, the nanosheet stack including alternating sacrificial and channel layers, the channel layers providing nanosheet channels for nanosheet field-effect transistors. The method also includes forming vertical fins in the nanosheet stack and a portion of the substrate, and forming indents in sidewalls of the sacrificial layers at sidewalls of the vertical fins. The method further includes forming nanosheet extension regions in portions of the channel layers which extend from the indented sidewalls of the sacrificial layers to the sidewalls of the vertical fins, the nanosheet extension regions increasing in thickness from the indented sidewalls of the sacrificial layers to the sidewalls of the vertical fins. The method further includes forming inner spacers using a conformal deposition process that forms air gaps in spaces between the nanosheet extension regions and the indented sidewalls of the sacrificial layers.

Claims20

Dependent claims

A method of forming a semiconductor structure, comprising:

forming a nanosheet stack over a substrate, the nanosheet stack comprising alternating sacrificial layers and channel layers, the channel layers providing nanosheet channels for one or more nanosheet field-effect transistors;
forming one or more vertical fins in the nanosheet stack and at least a portion of the substrate;
forming indents in sidewalls of the sacrificial layers at vertical sidewalls of the one or more vertical fins;
forming nanosheet extension regions in portions of the channel layers which extend from the indented sidewalls of the sacrificial layers to the vertical sidewalls of the one or more vertical fins, the nanosheet extension regions increasing in thickness from a first thickness proximate the indented sidewalls of the sacrificial layers to a second thickness proximate the vertical sidewalls of the one or more vertical fins;
and
forming inner spacers using a conformal deposition process that forms air gaps in spaces between the nanosheet extension regions and the indented sidewalls of the sacrificial layers.

3 more elements

A semiconductor structure, comprising:

a substrate;
one or more vertical fins disposed over a top surface of the substrate, the one or more vertical fins comprising a first semiconductor layer and a nanosheet channel stack disposed over the first semiconductor layer, the nanosheet channel stack comprising alternating gate stack layers and channel layers providing nanosheet channels for one or more nanosheet field-effect transistors;
the gate stack layers having indented sidewalls;
the channel layers comprising nanosheet extension regions extending from the indented sidewalls of the gate stack layers to the vertical sidewalls of the one or more vertical fins, the nanosheet extension regions increasing in thickness from a first thickness proximate the indented sidewalls of the gate stack layers to a second thickness proximate the vertical sidewalls of the one or more vertical fins;
inner spacers disposed in a first portion of spaces between the nanosheet extension regions, the indented sidewalls of the gate stack layers and the vertical sidewalls of the one or more vertical fins;
and
air gaps disposed in a second portion of the spaces between the nanosheet extension regions, the indented sidewalls of the gate stack layers and the vertical sidewalls of the one or more vertical fins.

4 more elements

An integrated circuit comprising:

a nanosheet field-effect transistor structure comprising:
a substrate;
one or more vertical fins disposed over a top surface of the substrate, the one or more vertical fins comprising a first semiconductor layer and a nanosheet channel stack disposed over the first semiconductor layer, the nanosheet channel stack comprising alternating gate stack layers and channel layers providing nanosheet channels for one or more nanosheet field-effect transistors;
the gate stack layers having indented sidewalls;
the channel layers comprising nanosheet extension regions extending from the indented sidewalls of the gate stack layers to the vertical sidewalls of the one or more vertical fins, the nanosheet extension regions increasing in thickness from a first thickness proximate the indented sidewalls of the gate stack layers to a second thickness proximate the vertical sidewalls of the one or more vertical fins;
inner spacers disposed in a first portion of spaces between the nanosheet extension regions, the indented sidewalls of the gate stack layers and the vertical sidewalls of the one or more vertical fins;
and
air gaps disposed in a second portion of the spaces between the nanosheet extension regions, the indented sidewalls of the gate stack layers and the vertical sidewalls of the one or more vertical fins.

5 more elements

Dependencies are inferred from the claim text.

Source/drain extension regions and air spacers for nanosheet field-effect transistor structures

Life of this patent

Source/drain extension regions and air spacers for nanosheet field-effect transistor structures

Life of this patent

Abstract

Claims20