Structure for capacitor protection, package structure, and method of forming package structure

A package structure, comprising:

• a substrate;
• a chip, arranged to cover a part of a surface of the substrate;
• a metal thermal conducting layer, arranged on a top surface of the chip;
• a capacitive structure, arranged on another part of the surface of the substrate, wherein the another part of the surface of the substrate is not covered by the chip, and the capacitive structure is arranged to be independent from the chip;
• a cover, comprising a first cover layer and a second cover layer connected to the first cover layer, wherein the first cover layer defines a first opening extending through the first cover layer, the second cover layer is arranged on a bottom of the first cover layer and perpendicular to the first cover layer, the first opening is further defined to extend through the second cover layer, the first cover layer is arranged on the capacitive structure, the chip is received in the first opening, and the second cover layer is arranged between the capacitive structure and the chip and is fixed to the substrate;
• and
• a heat dissipating cover and a connection layer, wherein the heat dissipating cover is arranged on the substrate and defines a cavity to receive the chip, the metal thermal conducting layer, the capacitive structure, and the cover;
• and the connection layer is arranged on an edged region of the surface of the substrate and arranged to fix the heat dissipating cover to the substrate.

A method of forming a package structure, comprising:

• providing a substrate, wherein a part of a surface of the substrate is covered by a chip, another part of the surface of the substrate, which is not covered by the chip, is covered by a capacitive structure, and the capacitive structure and the chip are independent from each other;
• providing a cover, wherein the cover comprises a first cover layer and a second cover layer connected to the first cover layer, the first cover layer defines a first opening extending through the first cover layer, the second cover layer is arranged at a bottom of the first cover layer and perpendicular to the first cover layer, and the first opening further extends through the second cover;
• arranging the cover on the substrate, wherein the first cover layer is arranged on the capacitive structure, the chip is received in the first opening, and the second cover layer is arranged between the capacitive structure and the chip, and is fixed to the substrate;
• after arranging the cover on the substrate, forming a metal thermal conducting layer on a top surface of the chip;
• and
• after forming the metal thermal conducting layer, performing high-temperature reflow soldering, wherein a temperature set during the high-temperature reflow soldering is greater than a melting point of the metal thermal conducting layer.