Resistive memory cell having a single fin

A method for fabricating a semiconductor device including a resistive memory cell having a single fin, comprising:

• concurrently forming a vertical transistor and a resistive element on a base substrate, including:
• forming a sidewall spacer on at least one fin formed on a bottom source/drain layer disposed on the base substrate;
• forming first and second shallow trench isolation (STI) regions on the base substrate adjacent to the bottom source/drain layer;
• forming a first gate structure corresponding to a gate of the vertical transistor on the first STI region and a second gate structure corresponding to an electrode of the resistive element on the second STI region;
• forming a top source/drain layer on the at least one fin;
• and
• forming a plurality of contacts, including forming a wordline contact corresponding to the first gate structure, a bitline contact corresponding to the top source/drain region and a source line contact corresponding to the second gate structure.

A semiconductor device including a resistive memory cell having a single fin, comprising:

• a base substrate;
• a bottom source/drain layer disposed on the base substrate;
• a fin disposed on the bottom source/drain layer;
• a top source/drain layer disposed on the fin;
• a first gate structure corresponding to a gate of a vertical transistor and a second gate structure corresponding to an electrode of a resistive element;
• and
• a plurality of contacts, including a wordline contact corresponding to the first gate structure, a bitline contact corresponding to the top source/drain region and a source line contact corresponding to the second gate structure.