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US 2020/0286953 A1Published application
Memory unit
AssigneeSony Semiconductor Solutions Corporation
InventorsMakoto KITAGAWA, Yoshiyuki SHIBAHARA, Haruhiko TERADA, Yotaro MORI
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Abstract
In a memory unit according to an embodiment of the present disclosure, a memory cell array is configured, when, of a plurality of memory cells, multiple first memory cells whose corresponding fourth wiring line and first wiring line are different from one another are simultaneously accessed, to allow for simultaneous access to the multiple first memory cells, without allowing for simultaneous access to memory cells corresponding to the fourth wiring line shared by the first memory cells.
Claims12
A memory unit comprising:
- a memory cell array;
- and
- a driving circuit that accesses the memory cell array,
- the memory cell array including
- pluralities of first wiring lines that extend in a first direction, and are disposed to be aligned in a second direction orthogonal to the first direction and in a third direction orthogonal to the first direction and the second direction,
- a plurality of second wiring lines that extends in the first direction, and is disposed to be aligned in the second direction,
- pluralities of third wiring lines that extend in the third direction, and are disposed to be aligned in the first direction and in the second direction, and are also disposed to go through a gap between two first wiring lines adjacent to each other in the second direction when viewed from the third direction,
- a plurality of resistance-varying memory cells, one memory cell being provided at each of respective points at which the third wiring lines and the first wiring lines are opposed to each other,
- a plurality of transistors each having a gate coupled to the corresponding second wiring line, one transistor being provided for each of the third wiring lines, and
- a plurality of fourth wiring lines that extends in the second direction, and is disposed to be aligned in the first direction, one fourth wiring line being provided for multiple third wiring lines disposed to be aligned in the second direction, and each of the fourth wiring lines being coupled to the corresponding multiple third wiring lines through the transistors,
- wherein when, of the plurality of memory cells, multiple first memory cells whose corresponding fourth wiring line and first wiring line are different from one another are simultaneously accessed, the memory cell array allows for simultaneous access to the multiple first memory cells, without allowing for simultaneous access to memory cells corresponding to the fourth wiring lines shared by the first memory cells.
8 more elements
A memory unit comprising:
- a memory cell array;
- and
- a driving circuit that accesses the memory cell array,
- the memory cell array including
- pluralities of first wiring lines that extend in a first direction, and are disposed to be aligned in a second direction orthogonal to the first direction and in a third direction orthogonal to the first direction and the second direction,
- a plurality of second wiring lines that extends in the first direction, and is disposed to be aligned in the second direction,
- pluralities of third wiring lines that extend in the third direction, and are disposed to be aligned in the first direction and in the second direction, and are also disposed to go through a gap between two first wiring lines adjacent to each other in the second direction when viewed from the third direction,
- a plurality of resistance-varying memory cells, one memory cell being provided at each of respective points at which the third wiring lines and the first wiring lines are opposed to each other,
- a plurality of transistors each having a gate coupled to the corresponding second wiring line, one transistor being provided for each of the third wiring lines, and
- a plurality of fourth wiring lines that extends in the second direction, and is disposed to be aligned in the first direction, one fourth wiring line being provided for multiple third wiring lines disposed to be aligned in the second direction, and each of the fourth wiring lines being coupled to the corresponding multiple third wiring lines through the transistors,
- wherein the driving circuit simultaneously accesses, of the plurality of memory cells, multiple first memory cells whose corresponding fourth wiring line is shared by one another and corresponding first wiring line is different from one another.
8 more elements
Dependencies are inferred from the claim text.