Methods for forming three-dimensional memory devices

A method for forming a three-dimensional (3D) memory device, comprising:

• forming a first channel structure and a second channel structure each extending vertically through a memory stack comprising interleaved conductor layers and dielectric layers above a first substrate;
• forming a first semiconductor plug at one end of the first channel structure and a second semiconductor plug at one end of the second channel structure;
• forming a semiconductor connection above the memory stack and in contact with the first semiconductor plug of the first channel structure and the second semiconductor plug of the second channel structure;
• forming a peripheral device on a second substrate;
• joining the first substrate and the second substrate;
• removing the first substrate to expose another end of the first channel structure and another end of the second channel structure;
• forming another first semiconductor plug at the another end of the first channel structure and another second semiconductor plug at the another end of the second channel structure;
• and
• forming a bit line contact in contact with another first semiconductor plug of the first channel structure and a source line contact in contact with the another second semiconductor plug of the second channel structure.

A method for forming a three-dimensional (3D) memory device, comprising:

• forming a first channel structure and a second channel structure each extending vertically through a memory stack comprising interleaved conductor layers and dielectric layers above a substrate;
• forming a first semiconductor plug at one end of the first channel structure and a second semiconductor plug at one end of the second channel structure;
• forming a semiconductor connection above the memory stack and in contact with the first semiconductor plug of the first channel structure and the second semiconductor plug of the second channel structure;
• joining the substrate and a carrier wafer;
• removing the substrate to expose another end of the first channel structure and another end of the second channel structure;
• forming another first semiconductor plug at the another end of the first channel structure and another second semiconductor plug at the another end of the second channel structure;
• and
• forming a bit line contact in contact with another first semiconductor plug of the first channel structure and a source line contact in contact with the another second semiconductor plug of the second channel structure.