Integrated assemblies having transistor body regions coupled to carrier-sink-structures; and methods of forming integrated assemblies

An integrated assembly, comprising:

• a lower carrier-sink-structure;
• first comparative digit lines over the lower carrier-sink-structure;
• first source/drain regions over the first digit lines and being coupled with the first digit lines;
• vertically-extending first pillars over the first source/drain regions;
• each of the first pillars comprising a first transistor body region and a second source/drain region;
• capacitors coupled with the second source/drain regions;
• vertically-extending second pillars over the capacitors;
• each of the second pillars comprising a third source/drain region and a second transistor body region over the third source/drain region;
• the third source/drain regions being coupled with the second capacitor nodes;
• fourth source/drain regions over the second transistor body regions;
• second comparative digit lines over the fourth source/drain regions and being coupled with the fourth source/drain regions;
• individuals of the first comparative digit lines being paired with individuals of the second comparative digit lines in a plurality of first/second comparative digit line sets;
• the comparative first and second digit lines of each of the first/second comparative digit line sets extending to a sense amplifier configured to compare electrical properties of the first and second comparative digit lines within the first/second comparative digit line set;
• an upper carrier-sink-structure over the second digit lines;
• first extensions extending from the lower carrier-sink-structure to the first transistor body regions;
• the first extensions being configured to drain excess carriers from the first transistor body regions to the lower carrier-sink-structure;
• second extensions extending from the upper carrier-sink-structure to the second transistor body regions;
• the second extensions being configured to drain excess carriers from the second transistor body regions to the upper carrier-sink-structure;
• and
• gates having components adjacent the first and second transistor body regions.

A method of forming an integrated assembly, comprising:

• forming a stack comprising, in ascending order, a first semiconductor material, an insulative material, a digit line material, and a second semiconductor material;
• the first semiconductor material being either p-type doped or n-type doped, and the second semiconductor material being the other of p-type doped and n-type doped;
• patterning the insulative material, the digit line material, and the second semiconductor material into rails extending along a first direction;
• the rails being spaced from one another by gaps;
• regions of the first semiconductor material being exposed along bottom peripheries of the gaps;
• the rails having sidewalls along the gaps;
• the patterned digit line material within the rails being digit lines;
• forming first insulative spacers along the sidewalls of the rails;
• forming semiconductor extensions along the first insulative spacers;
• the semiconductor extensions and the first insulative spacers narrowing the gaps;
• forming second insulative spacers within the narrowed gaps;
• forming a planarized surface extending across the rails, the first insulative spacers, the semiconductor extensions and the second insulative spacers;
• forming third semiconductor material over and directly against the planarized surface;
• forming slits extending through the third semiconductor material to the second insulative spacers;
• the slits extending linearly along the first direction;
• forming insulative panels within the slits;
• forming trenches extending through the third semiconductor material and the insulative panels;
• the trenches extending along a second direction which crosses the first direction;
• the trenches patterning the third semiconductor material into pillars comprising transistor body regions;
• the second semiconductor material comprising first source/drain regions under the transistor body regions;
• forming gate dielectric material along sidewalls of the transistor body regions;
• forming wordlines along the gate dielectric material;
• the wordlines extending along the second direction;
• forming second source/drain regions within upper regions of the pillars;
• forming storage elements coupled with the second source/drain regions;
• wherein the first source/drain regions, the second source/drain regions and the transistor body regions are together incorporated into access transistors;
• wherein the access transistors and the storage elements are incorporated into memory cells of a memory array;
• and
• wherein the extensions are configured to drain excess carriers from the transistor body regions to the first semiconductor material during operation of the memory cells.