Hybrid interposer and semiconductor package

A hybrid interposer comprising:

• a core substrate having at least one cavity and having through-vias connecting upper and lower surfaces thereof to each other;
• a passive component accommodated in the at least one cavity;
• a first insulating layer disposed on the upper surface of the core substrate and encapsulating passive component in the at least one cavity;
• a first wiring layer disposed on the first insulating layer and connected to the through-vias and the passive component;
• a second insulating layer disposed on the lower surface of the core substrate;
• a second wiring layer disposed on a lower surface of the second insulating layer and connected to the through-vias;
• and
• a connection structure including an insulating member disposed on the upper surface of the core substrate and a redistribution layer disposed on the insulating member and connected to the first wiring layer.

A semiconductor package comprising:

• an interposer substrate including a core substrate and a connection structure, the core substrate having cavities in which passive components are embedded and having through-vias connecting upper and lower surfaces of the core substrate to each other, and the connection structure including an insulating member disposed on the upper surface of the core substrate and a redistribution layer disposed on the insulating member;
• semiconductor chips disposed on an upper surface of the connection structure and including connection pads connected to the redistribution layer;
• a first insulating layer disposed between the core substrate and the connection structure and encapsulating the passive component in the at least one cavity;
• a first wiring layer disposed on the first insulating layer and connecting the through-vias and the passive component to the redistribution layer;
• a second insulating layer disposed on the lower surface of the core substrate;
• and
• a second wiring layer disposed on a lower surface of the second insulating layer and connected to the through-vias,
• wherein one of the cavities overlaps with two or more of the semiconductor chips adjacent to each other, in a plan view.