Semiconductor chips including through electrodes and methods of testing the through electrodes

A semiconductor chip comprising:

• a first drive circuit configured to include a first inverter group connected to a plurality of through electrodes, configured to sequentially drive the plurality of through electrodes to a first pattern and a second pattern to generate a plurality of test data, and configured to generate a detection signal according to comparison results of the plurality of test data based on first to third test signals;
• and
• a second drive circuit configured to include a second inverter group connected to the plurality of through electrodes,
• wherein a plurality of inverters included in the first and second inverter groups are selectively turned on according to the comparison results of the plurality of test data based on the first and second test signals.

A test method comprising the steps of:

• generating a plurality of test data by sequentially driving a first pattern of logic levels and a second pattern of logic levels through a plurality of through electrodes connecting a first semiconductor device to a second semiconductor device while in a test mode;
• comparing logic levels of the plurality of test data to generate a plurality of comparison signals;
• driving the plurality of through electrodes with a plurality of inverters which are selectively turned on based on the plurality of comparison signals;
• and
• detecting a detection signal generated by the plurality of inverters selectively turned on and by the plurality of through electrodes to verify that the plurality of through electrodes operated normally or that at least one through electrode from the plurality of through electrodes operated abnormally.