Forming a backside ground or power plane in a stacked vertical transport field effect transistor

Abstract

Techniques facilitating forming a backside ground or power plane in stacked vertical transport field effect transistor are provided. A semiconductor structure can comprise a first field effect transistor (FET). The semiconductor structure can also comprise a second FET. The first FET can be vertically stacked on a first surface of the second FET. The second FET can be electrically coupled to a conductive plane on a second surface of the second FET, the second surface being opposite to the first surface.

Dependencies are inferred from the claim text.