Methods of forming an ic product comprising transistor devices with different threshold voltage levels

A method of forming first and second transistors on first and second active regions, respectively, of a semiconductor substrate, the first and second transistors having first and second threshold voltages, respectively, that are different from one another, the method comprising:

• forming a conformal high-k gate insulation layer within first and second replacement gate cavities for the first and second transistors, respectively;
• forming a conformal sacrificial metal-containing (SMCM) layer above the conformal high-k gate insulation layer within each of the first and second replacement gate cavities;
• removing the conformal SMCM layer positioned within the first replacement gate cavity and above the first active region while leaving the conformal SMCM layer in position within the second replacement gate cavity and above the second active region;
• forming a first conformal metal-containing material (MCM) layer above the conformal high-k gate insulation layer within the first replacement gate cavity and above the conformal SMCM layer in position within the second replacement gate cavity;
• removing the first conformal MCM layer and the conformal SMCM layer positioned within the second replacement gate cavity and above the second active region while leaving the first conformal MCM layer within the first replacement gate cavity and above the first active region;
• and
• forming a second conformal metal-containing material (MCM) layer above the first conformal MCM layer positioned within the first replacement gate cavity and above the conformal high-k gate insulation layer positioned within the second replacement gate cavity.

A method of forming first and second transistors on first and second active regions, respectively, of a semiconductor substrate, the first and second transistors having first and second threshold voltages, respectively, that are different from one another, the method comprising:

• forming first and second replacement gate cavities for the first and second transistors, respectively;
• forming a conformal high-k gate insulation layer within each of the first and second replacement gate cavities;
• forming a conformal sacrificial metal-containing (SMCM) layer on and in contact with the conformal high-k gate insulation layer within each of the first and second replacement gate cavities;
• forming a first patterned etch mask that covers the second transistor and leaves the first transistor exposed for further processing;
• with the first patterned etch mask in position, removing the conformal SMCM layer positioned within the first replacement gate cavity and above the first active region while leaving the conformal SMCM layer in position within the second replacement gate cavity and above the second active region;
• removing the first patterned etch mask so as to expose both the first and second transistors for further processing;
• forming a first conformal metal-containing material (MCM) layer on and in contact with the conformal high-k gate insulation layer within the first replacement gate cavity and on and in contact with the conformal SMCM layer in position within the second replacement gate cavity;
• forming a second patterned etch mask that covers the first transistor and leaves the second transistor exposed for further processing;
• with the second patterned etch mask in position, removing the first conformal MCM layer positioned within the second replacement gate cavity and above the second active region and the conformal SMCM layer positioned within the second replacement gate cavity and above the second active region;
• removing the second patterned etch mask so as to expose both the first and second transistors for further processing;
• and
• forming a second conformal metal-containing material (MCM) layer on and in contact with the first conformal MCM layer positioned within the first replacement gate cavity and on and in contact with the conformal high-k gate insulation layer positioned within the second replacement gate cavity.