Method of Semiconductor Integrated Circuit Fabrication

A device, comprising:

• a gate located over a substrate;
• a source/drain located in the substrate;
• a first metal plug located over the source/drain;
• a first hard mask located over the gate;
• a second hard mask located over the first metal plug;
• a first dielectric layer located over the substrate and separating the first metal plug and the gate;
• a second dielectric layer located over the first dielectric layer;
• a second metal plug located over the gate, wherein the first hard mask is in contact with a lower portion of the second metal plug, and wherein the second dielectric layer is in contact with an upper portion of the second metal plug;
• and
• a third metal plug located over the first metal plug, wherein the second hard mask is in contact with a lower portion of the third metal plug, and wherein the second dielectric layer is in contact with an upper portion of the third metal plug.

A device, comprising:

• a first gate and a second gate each formed over a substrate;
• a plurality of first hard masks formed over the first gate and the second gate;
• a first source/drain and a second source/drain each located in the substrate;
• a plurality of first metal plugs formed over the first source/drain and the second source/drain;
• a plurality of second hard masks formed over the first metal plugs;
• and
• a plurality of second metal plugs, wherein a first one of the second metal plugs is aligned with the first gate and extends vertically through one of the first hard masks that is formed over the first gate, and wherein a second one of the second metal plugs is aligned with the first source/drain and extends vertically through another one of the second hard masks that is formed over one of the first metal plugs that is formed over the first source/drain, and wherein none of the second metal plugs is formed over the second gate or the second source/drain.