Fabricating vias with lower resistance
AssigneeInternational Business Machines Corporation
InventorsBaozhen Li, Chih-Chao Yang, Andrew Tae Kim
Life of this patent
Estimating the term…
Abstract
An interconnection for a device in an integrated circuit includes a substrate on which a first metal line is embedded in a first dielectric layer. A via gouge is etched in the first metal line. A second dielectric layer is deposited over the first metal line and the first dielectric layer. A first via recess is etch through the second dielectric layer where the first via recess aligned to the via gouge. A second metal layer is deposited in the first via recess and the via gouge, forming a first via.
Claims18
A method for fabricating an interconnection for a device in an integrated circuit comprising:
- providing a substrate including a first metal line embedded in a first dielectric layer;
- etching a via gouge in the first metal line;
- depositing a second dielectric layer over the first metal line and the first dielectric layer;
- etching a first via recess through the second dielectric layer, the first via recess aligned to the via gouge;
- and
- depositing a second metal layer in the first via recess and the via gouge, forming a first via.
A device comprising:
- a substrate including a first metal line embedded in a first dielectric layer;
- a via gouge in the first metal line, the via gouge having a first width;
- a capping layer over the first metal line and the first dielectric layer;
- a second dielectric layer over the first metal line and the first dielectric layer in which a first via and a metal line pattern recess are etched, the first via recess aligned to the via gouge and having a second width less than the first width;
- a barrier layer over sides of the metal line pattern and first via recesses and a central portion of a top surface of the via gouge;
- and
- a first via and a second metal line pattern respectively in the first via and the metal line pattern recess in the second dielectric layer;
- wherein the barrier layer meets the capping layer along a top surface of the via gouge.
A device comprising:
- a substrate including a first metal line pattern embedded in a first dielectric layer;
- a via gouge in a first metal line of the first metal line pattern;
- a capping layer over the first metal line pattern and the first dielectric layer;
- a second dielectric layer over the first metal line and the first dielectric layer in which a first via recess and a second via recess are etched, the first via recess aligned to the via gouge and the second via recess aligned to a planar top surface of a second metal line of the first metal line pattern;
- a barrier layer over sides of the via recesses and the via gouge;
- a first via and a second via respectively in the first via and the second via recesses in the second dielectric layer;
- and
- wherein the first via is formed in a critical area and the second via is formed in a non-critical area of the device.
Dependencies are inferred from the claim text.