Erase control circuit and method of non-volatile semiconductor memory device, and non-volatile semiconductor memory device

Abstract

The disclosure controls the erase voltage with higher accuracy than the related art when erasing data in a non-volatile semiconductor memory device. An control circuit for controlling an erase voltage includes: a slope adjustment circuit that controls a slope having a step shape by controlling a step voltage, a target voltage, and a step width of the erase voltage. The slope adjustment circuit repeatedly increases the erase voltage by the step voltage for each predetermined clock pulse control signal to the target voltage based on the step voltage and the target voltage, and outputs the clock pulse control signal to the erase voltage generation circuit by repeatedly clocking each time interval corresponding to the step width based on the step width.

Dependencies are inferred from the claim text.