Seu stabilized memory cells

A single-event-upset (SEU) stabilized memory cell comprising:

• a first p-channel transistor coupled between a first voltage supply node and a first complementary output node;
• a first n-channel transistor coupled between the first complementary output node and a second voltage supply node;
• a second p-channel transistor coupled between the first voltage supply node and a second complementary output node, gates of the first p-channel transistor and the first n-channel transistor connected together and coupled to the second complementary output node;
• a second n-channel transistor coupled between the second complementary output node and the second voltage supply node, gates of the second p-channel transistor and the second n-channel transistor connected together and coupled to the first complementary output node through a first series-connected pair of vertical resistors,
• wherein the first series-connected pair of vertical resistors is formed as a vertical stack that includes a first electrode for a first ReRAM device disposed over a metal segment of a first metallization layer in the integrated circuit, a switching layer for the first ReRAM device disposed over the first electrode for the first ReRAM device, a second electrode for both the first ReRAM device and a second ReRAM device disposed over the switching layer for the first ReRAM device, a switching layer for the second ReRAM device disposed over the second electrode for the first and second ReRAM devices, and a first electrode for the second ReRAM device disposed over the switching layer for the second ReRAM device.

A single-event-upset (SEU) stabilized memory cell comprising:

• a latch portion including a cross-coupled latch;
• and
• at least one cross coupling circuit path in the latch portion including a first series-connected pair of vertical resistors formed as a vertical stack,
• wherein the vertical stack comprises a first electrode for a first ReRAM device disposed over a metal segment of a first metallization layer in the integrated circuit, a switching layer for the first ReRAM device disposed over the first electrode for the first ReRAM device, a second electrode for both the first ReRAM device and a second ReRAM device disposed over the switching layer for the first ReRAM device, a switching layer for the second ReRAM device disposed over the second electrode for the first and second ReRAM devices, and a first electrode for the second ReRAM device disposed over the switching layer for the second ReRAM device.

A method for operating an array of SEU stabilized memory cells in an integrated circuit, the method comprising:

• applying power to the integrated circuit at a reduced supply voltage;
• setting cross-coupled latches of the memory cells to an initial pre-determined state;
• loading into the memory cells data from ReRAMs in PROMs associated with the memory cells;
• writing corrected data from an error memory into already-known locations at which ReRAM based PROM cells have failed;
• performing a verify operation to determine whether the memory cells all contain correct data;
• if the memory cells all contain correct data, raising the supply voltage to an operating level and turning on a core of the integrated circuit;
• if all of the memory cells do not contain correct data, using a forward error correction (FEC) code to determine locations of incorrect data;
• writing correct data calculated from the FEC code into cross-coupled latches of memory cells identified as having incorrect data;
• writing the location of the incorrect data and the corrected data into the error memory;
• and
• re-performing a verify operation to determine whether the memory cells all contain correct data.