Initialisation of a Storage Device
AssigneeArm Limited
InventorsWei Wang, Shidhartha Das
Life of this patent
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Abstract
There is provided a system comprising: a storage device having a storage portion comprising a plurality of bitcells coupled to respective first signal lines and second signal lines and control logic to alter a memory state of the plurality of bitcells via the first signal lines and second signal lines; a memory controller coupled to the storage device to transmit one or more initialisation signals to the storage device; wherein the storage device is to initialise the storage portion over a clock cycle in response to the one or more initialisation signals.
Claims24
A system comprising:
- a storage device having a storage portion comprising a plurality of bitcells coupled to respective first signal lines and second signal lines and control logic to alter a memory state of the plurality of bitcells via the first signal lines and the second signal lines;
- a memory controller coupled to the storage device to transmit one or more encoded initialisation signals to the storage device;
- wherein the storage device is configured to decode the one or more encoded initialisation signals and initialise the storage portion over a clock cycle in response to the one or more decoded initialisation signals.
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21-24. (canceled)
A method of initialising a portion of storage on a storage device, the method comprising:
- generating, at a memory controller, encoded initialisation signals based, at least in part, on instructions from a bus master to initialise the portion of storage, the portion of storage comprising a plurality of bitcells coupled to respective first signal lines and second signal lines;
- decoding, at the storage device, the encoded initialisation signals;
- and
- initialising, at the storage device, the portion of storage over a clock cycle in response to the decoded initialisation signals.
26-27. (canceled)
A storage device, having an addressable portion comprising a plurality of bitcells coupled to respective first signal lines and second signal lines, and control logic to alter a memory state of the bitcells;
- wherein the storage device is configured to:
- decode one or more initialisation signals from a memory controller;
- and
- initialise the plurality of bitcells over a clock cycle in response to the decoded one or more initialisation signals.
Dependencies are inferred from the claim text.