Semiconductor memory device

A semiconductor memory device comprising:

• a substrate;
• first and second planes of memory cells, that are above and parallel to a substrate surface;
• a plurality of first wirings, each extending in a first direction, in a third plane that is parallel to the substrate surface and between the substrate surface and the first plane of memory cells;
• a plurality of second wirings, each extending in a second direction that crosses the first direction, in a fourth plane that is parallel to the substrate surface and between the first plane of memory cells and the second plane of memory cells;
• a plurality of third wirings, each extending in the first direction, in a fifth plane that is parallel to the substrate surface and above the second plane of memory cells;
• a first multiplexer that extends in the second direction and is provided in a first rectangular box region, side ends of which are defined by the memory cells of the first and second planes in the first and second directions;
• a plurality of first connection wirings, each extending in a third direction, which crosses the first and second directions, to connect the first multiplexer to one of the plurality of first wirings;
• a second multiplexer that extends in the second direction and is provided in a second rectangular box region which is adjacent to the first rectangular box region in the first direction;
• a plurality of second connection wirings, each extending in the third direction to connect the second multiplexer to one of the plurality of third wirings;
• a third multiplexer that extends in the first direction and is provided in the first rectangular box region;
• and
• a plurality of third connection wirings, each extending in the third direction to connect the third multiplexer to one of the plurality of second wirings.

A semiconductor memory device, comprising:

• a substrate;
• a plurality of first wirings above the substrate, each extending in a first direction;
• a plurality of second wirings above the plurality of first wirings, each extending in a second direction that crosses the first direction;
• a plurality of third wirings above the plurality of second wirings, each extending in the first direction;
• a first plane of memory cells between the plurality of first wirings and the plurality of second wirings;
• a second plane of memory cells between the plurality of second wirings and the plurality of third wirings;
• a plurality of fourth wirings above the substrate, each extending in the first direction;
• a plurality of fifth wirings above the plurality of fourth wirings, each extending in the second direction;
• a plurality of sixth wirings above the plurality of fifth wirings, each extending in the first direction;
• a third plane of memory cells between the plurality of fourth wirings and the plurality of fifth wirings;
• a fourth plane of memory cells between the plurality of fifth wirings and the plurality of sixth wirings;
• a first multiplexer that extends in the second direction, is connected to the plurality of first wirings, and is provided in a first rectangular box region, side ends of which are defined by the memory cells of the first and second planes in the first and second directions;
• a second multiplexer that extends in the first direction, is connected to the plurality of second wirings, and is provided in the first rectangular box region;
• a third multiplexer that extends in the second direction, is connected to the plurality of fourth wirings, and is provided in a second rectangular box region, side ends of which are defined by the memory cells of the third and fourth planes in the first and second directions;
• and
• a fourth multiplexer that extends in the first direction, is connected to the plurality of fifth wirings, and is provided in the second rectangular box region.