In-memory computation device with inter-page and intra-page data circuits

An in-memory computation device, comprising:

• a memory including a plurality of blocks B(n), where n ranges from 0 to N−1;
• a plurality of page output circuits connected to the memory, a page output circuit PO(n) in the plurality of page output circuits generating a page output vector VO(n), and being operatively coupled to a block B(n) in the plurality of blocks;
• a plurality of page input circuits connected to the memory, a page input circuit PI(n) in the plurality of page input circuits receiving a page input vector VI(n), and generating input voltages in response to the page input vector VI(n), and being operatively coupled to the block B(n);
• a plurality of bit line bias circuits connected to the plurality of blocks, a bit line bias circuit Y(n) in the plurality of bit line bias circuits being operatively coupled to the block B(n) in the plurality of blocks, and to the page input circuit PI(n) in the plurality of page input circuits, and biasing the bit lines in the block B(n) in response to input voltages generated by the page input circuit PI(n);
• a data bus system;
• and
• data circuits configurable connect the page input circuit PI(n) to one or more of the page output circuit PO(n), a page output circuit PO(n−1), and the data bus system to select a source for the page input vector VI(n) in a sensing cycle.

An in-memory computation device, comprising:

• a memory including a plurality of blocks B(n), where n ranges from 0 to N−1;
• a plurality of page output circuits connected to the memory, a page output circuit PO(n) in the plurality of page output circuits generating a page output vector VO(n), and being operatively coupled to a block B(n) in the plurality of blocks;
• a plurality of page input circuits connected to the memory, a page input circuit PI(n) in the plurality of page input circuits receiving a page input vector VI(n), and generating input voltages in response to the page input vector VI(n), and being operatively coupled to the block B(n);
• a plurality of word line drivers connected to the plurality of blocks, a word line driver WD(n) in the plurality of word line drivers being operatively coupled to the block B(n) in the plurality of blocks, and to the page input circuit PI(n) in the plurality of page input circuits, and biasing the word lines in block B(n) in response to input voltages generated by the page input circuit PI(n);
• a data bus system;
• and
• data circuits configurable connect page input circuit PI(n) to one or more of page output circuit PO(n), page output circuit PO(n−1), and the data bus system to select a source for the page input vector VI(n) in a sensing cycle.