Row based memory write assist and active sleep bias
AssigneeIntel Corporation
InventorsZheng Guo, Clifford L. Ong, Eric A. Karl
Life of this patent
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Abstract
An apparatus is provided which comprises: an interconnect comprising poly extending in a first direction; a power supply rail extending in a second direction, wherein the second direction is parallel to the first direction; and a memory array organized in rows and columns, wherein the rows are orthogonal to the columns, wherein the first and second directions are parallel to the rows of the memory array, wherein the memory array comprises bit-cells (e.g., 6T SRAM bit-cells) that are organized such that there are no gap bit-cells in the array.
Claims21
(canceled)
An apparatus comprising:
- a first p-type transistor controllable by a low power mode, and coupled to a first supply node;
- a second p-type transistor coupled to a second power supply node and a third power supply node;
- a third p-type transistor coupled in parallel to the second p-type transistor;
- and
- a memory array organized in rows and columns, wherein the rows are orthogonal to the columns, wherein the third power supply node is coupled to a row or a group of rows of the memory array, wherein the third power supply node extends in a direction orthogonal to a direction of the columns.
An apparatus comprising:
- a memory array organized in rows and columns, wherein the rows are orthogonal to the columns;
- a first p-type transistor controllable by a first wake signal for a sector of the memory array, and coupled to a first supply node;
- a second p-type transistor coupled to a second power supply node and a third power supply node, wherein the second p-type transistor is controllable by a bias;
- a third p-type transistor coupled in parallel to the second p-type transistor;
- an n-type transistor coupled in series with the third p-type transistor, wherein the n-type device is coupled to a ground supply node;
- and
- a first NAND gate to control the third p-type transistor via the first wake signal and a pulse signal;
- and
- a second NAND gate to control the n-type transistor via the pulse signal and a second wake signal for a row of the memory array.
A system comprising:
- a processor core;
- a wireless interface communicatively coupled to the processor core;
- and
- a memory coupled to the processor core, wherein the memory includes:
- a first p-type transistor controllable by a low power mode, and coupled to a first supply node;
- a second p-type transistor coupled to a second power supply node and a third power supply node;
- a third p-type transistor coupled in parallel to the second p-type transistor;
- and
- a memory array organized in rows and columns, wherein the rows are orthogonal to the columns, wherein the third power supply node is coupled to a row or a group of rows of the memory array, wherein the third power supply node extends in a direction parallel to a direction of the rows.
Dependencies are inferred from the claim text.