Memory Structure with Bitline Strapping

An integrated circuit, comprising:

• an array of bitcells coupled between multiple pairs of bitlines including a first pair of bitlines and a second pair of bitlines;
• multiple pairs of ancillary lines disposed adjacent to the multiple pair of bitlines, wherein the multiple pairs of ancillary lines include a first pair of ancillary lines disposed adjacent to the first pair of bitlines and a second pair of ancillary lines disposed adjacent to the second pair of bitlines;
• and
• multiple pairs of passgates coupled between the multiple pairs of bitlines and the multiple pairs of ancillary lines.

A method, comprising:

• providing a memory structure having multiple bitcells disposed between multiple bitlines, multiple ancillary lines disposed adjacent to the multiple bitlines, and multiple passgates disposed between the multiple bitlines and the multiple ancillary lines;
• selectively activating the multiple passgates to facilitate reduction of resistance on the multiple bitlines during write operations;
• and
• selectively deactivating the multiple passgates facilitate reduction of capacitance on the multiple bitlines during read operations.