US 2020/0286546 A1Published application

Sub-amplifier, switching device and semiconductor device

AssigneeUltramemory Inc.

InventorYasutoshi YAMADA

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Abstract

Provided are a sub-amplifier, a switching device and a semiconductor device capable of simultaneously reading or writing many data items, while suppressing an increase in chip surface area, by using a single end signal line. A sub-amplifier SAP comprises: a first pre-charge circuit 110 that releases pre-charges of a pair of local wires LIOT/LIOB; a local inversion drive circuit 120 that, on the basis of a write signal WT, inverts and transfers write data to a sense amplifier SA from a main wire MIOB via one of the local wires LIOT/LIOB; a local non-inversion drive circuit 130 that, on the basis of the write signal WT, transfers the write data to the sense amplifier SA from the main wire MIOB via the other one of the local wires LIOT/LIOB; and a main inversion drive circuit 140 that, on the basis of a read signal RT, inverts and transfers read data to the main wire MIOB from one of the local wires LIOT/LIOB.

Claims9

Dependent claims

A sub-amplifier connected to a sense amplifier through a column switch and connected to a main wire through which write data and read data are transferred, the sub-amplifier comprising:

a pair of local wires that are connected to the sense amplifier and the column switch;
a first pre-charge circuit that is connected to each of the pair of local wires and releases pre-charging of the pair of local wires when the write data is written and the read data is read;
a local inversion drive circuit that is connected to one of the pair of local wires and the main wire and inverts and transfers the write data from the main wire to the sense amplifier through the one local wire on the basis of a write signal;
a local non-inversion drive circuit that is connected to the other of the pair of local wires and the main wire and transfers the write data from the main wire to the sense amplifier through the other local wire on the basis of the write signal;
and
a main inversion drive circuit that is connected to one of the pair of local wires and the main wire and inverts and transfers the read data from the one local wire to the main wire on the basis of a read signal.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/645,640Filed 11 Sep 2017
Published: 10 Sep 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

G11C 11/4091
Read-write [R-W] circuits: sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or…
G11C 7/06
Arrangements for writing information into, or reading information out from, a digital store: sense amplifiers; Associated circuits , e.g. timing…
G11C 7/065
Sense amplifiers; Associated circuits , e.g. timing or triggering circuits: differential amplifiers of latching type
G11C 7/1048
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data bus control circuits, e.g. precharging,…

Family

US 11,094,367 B2Related patent
US 2020/0286546 A1This patent

From the US filing history. Foreign family members aren’t listed.

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