Semiconductor memory device having clock generation scheme based on command

A dynamic random access memory (DRAM) device comprising:

• a clock buffer configured to receive a system clock (CK) having a first frequency;
• a data clock buffer configured to receive a data clock (WCK) having a second frequency which is higher than the first frequency;
• a command decoder configured to receive a first column address strobe (CAS) command for write operation and to receive a second column address strobe (CAS) command for read operation in synchronization with the system clock;
• and
• an internal data clock generating circuit configured to generate an internal data clock using the data clock in response to each of the first CAS command and the second CAS command, and to synchronize phase of the internal data clock with phase of the system clock by adjusting phase of the internal data clock,
• wherein the synchronization between the internal data clock and the system clock is performed after a first predetermined time from the first CAS command and after a second predetermined time from the second CAS command respectively, and the first predetermined time and the second predetermined time are different from each other, and the data clock starts to toggle after each of the first CAS command and the second CAS command is received.

A dynamic random access memory (DRAM) device comprising:

• a clock buffer configured to receive a system clock (CK) having a first frequency;
• a data clock buffer configured to receive a data clock (WCK) having a second frequency which is higher than the first frequency;
• a command decoder configured to receive a first CAS command for write operation in synchronization with the system clock and generate a first auto-sync signal after a first predetermined time from the first CAS command, and to receive a second CAS command for read operation in synchronization with the system clock and generate a second auto-sync signal after a second predetermined time from the second CAS command;
• and
• an internal data clock generating circuit configured to generate an internal data clock in response to each of the first auto-sync signal and the second auto-sync signal, the internal data clock including four-phase clock signals which are WCK_0, WCK_90, WCK_180 and WCK_270, the four-phase clock signals having phase differences of 90-degrees from one another, and one of the four-phase clock signals, WCK_0, is adjusted to be in-phase with the system clock,
• wherein the first predetermined time and the second predetermined time are different from each other, and the data clock starts to toggle after one of the first CAS command and the second CAS command is received.

A memory device comprising:

• a command decoder configured to generate an auto-sync signal in response to a column address strobe (CAS) command for writing data to a memory cell and reading data from a memory cell;
• and
• an internal data clock generating circuit configured to synchronize a phase of a second clock with a phase of a first clock in response to the auto-sync signal during write operation and read operation, wherein a frequency of the second clock is higher than a frequency of the first clock,
• wherein the auto-sync signal is delayed by a first predetermined time for writing data at a memory cell and a second predetermined time for reading data at a memory cell with respect to the CAS command, and
• wherein the second clock starts to toggle after the CAS command is received.