Ddr memory bus with a reduced data strobe signal preamble timespan

A memory chip, comprising:

• first register space to store a first on-die termination resistance value;
• second register space to store a second on-die termination resistance value;
• a first on-die termination resistance circuit to be coupled to a data strobe signal wire of a memory channel, whereupon, if a write operation is performed on the memory channel, the first on-die termination resistance circuit is to hold the data strobe signal wire's termination resistance at the first on-die termination resistance value during the write operation irrespective of whether or not the memory chip is a target of the write operation;
• and,
• a second on-die termination resistance circuit to be coupled to a data signal wire of the memory channel, whereupon:
• 1) if the memory chip is the target of the write operation, the second on-die termination resistance circuit is to select the first on-die termination resistance value for the data signal wire's termination resistance, 2) if the memory chip is not the target of the write operation, the second on-die termination resistance circuit is to not select the first on-die termination resistance value for the data signal wire's termination resistance.

A computing system, comprising:

• a plurality of processing cores;
• a graphics processing unit;
• a network interface;
• a memory module coupled to a memory controller by way of a memory channel, the memory module comprising a memory chip, the memory chip comprising:
• first register space to store a first on-die termination resistance value;
• second register space to store a second on-die termination resistance value;
• a first on-die termination resistance circuit to be coupled to a data strobe signal wire of the memory channel, whereupon, if a write operation is performed on the memory channel, the first on-die termination resistance circuit is to hold the data strobe signal wire's termination resistance at the first on-die termination resistance value during the write operation irrespective of whether or not the memory chip is a target of the write operation;
• and,
• a second on-die termination resistance circuit to be coupled to a data signal wire of the memory channel, whereupon:
• 1) if the memory chip is the target of the write operation, the second on-die termination resistance circuit is to select the first on-die termination resistance value for the data signal wire's termination resistance, 2) if the memory chip is not the target of the write operation, the second on-die termination resistance circuit is to not select the first on-die termination resistance value for the data signal wire's termination resistance.

A method, comprising:

• executing a write operation on a memory channel, the memory channel comprising a plurality of memory chips coupled to a data strobe signal wire and a data signal wire, the executing of the write operation comprising:
• driving the data strobe signal wire where a first set of the plurality of memory chips that are a target of the write operation and a second set of the plurality of memory chips that are not the target of the write operation do not change their respective termination resistance of the data strobe signal wire;
• and,
• driving the data signal wire where the first set of the plurality of the memory chips change their respective termination resistance of the data signal wire because they are the target of the write operation.