Dynamic random access memory (dram) cell, dram device and storage method

A dynamic random-access memory (DRAM) device, comprising:

• an address decoder, comprising a plurality of word lines and a plurality of bit lines intersecting each other to define a matrix, each of the bit lines configured to write and read data;
• and
• a plurality of DRAM cells distributed in the matrix, each of the DRAM cells coupled to at least one of the bit lines and at least one of the word lines,
• wherein the each of the DRAM cells comprises:
• a transistor having a gate electrically coupled to a word line of an address decoder and a drain electrically coupled to a bit line of the address decoder, wherein the bit line is coupled to a power supply voltage;
• a first diode;
• and
• a second diode, wherein an anode of the second diode is coupled to a cathode of the first diode at a first node, and a cathode of the second diode is coupled to an anode of the first diode at a second node, the first node is coupled to a source of the transistor, the second node is coupled to a node voltage,
• wherein an absolute value of a difference between the node voltage and the power supply voltage is smaller than a cut-in voltage of the first diode and the second diode.

A storage method for a dynamic random-access memory (DRAM) device, comprising:

• providing a DRAM device comprising an address decoder and a plurality of DRAM cells, the address decoder comprising a plurality of word lines and a plurality of bit lines intersecting each other to define a matrix, each of the bit lines configured to write and read data, the DRAM cells distributed in the matrix, each of the DRAM cells coupled to at least one of the bit lines and at least one of the word lines;
• and
• storing data on the first and second diodes,
• wherein the each of the DRAM cells comprises:
• a transistor having a gate electrically coupled to a word line of an address decoder and a drain electrically coupled to a bit line of the address decoder, wherein the bit line is coupled to a power supply voltage;
• a first diode;
• and
• a second diode, wherein an anode of the second diode is coupled to a cathode of the first diode at a first node, and a cathode of the second diode is coupled to an anode of the first diode at a second node, the first node is coupled to a source of the transistor, the second node is coupled to a node voltage,
• wherein an absolute value of a difference between the node voltage and the power supply voltage is smaller than a cut-in voltage of the first diode and the second diode.