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US 2020/0286539 A1Published application
Memory Cells and Arrays of Memory Cells
AssigneeMicron Technology, Inc.
InventorYasushi Matsubara
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Abstract
A memory cell comprises first, second, third, and fourth transistors individually comprising a transistor gate. First and second ferroelectric capacitors individually have one capacitor electrode elevationally between the transistor gates of the first, second, third, and fourth transistors. Other memory cells are disclosed, as are arrays of memory cells.
Claims25
A memory cell comprising:
- first, second, third, and fourth transistors;
- and
- first and second ferroelectric capacitors individually having one capacitor electrode at two elevationally-spaced levels, a ferroelectric capacitor insulator being between the one capacitor electrode and another capacitor electrode in one of the two levels and no ferroelectric capacitor insulator being between the one and the another capacitor electrodes in the other of the two levels.
A memory cell comprising:
- first, second, third, and fourth transistors individually comprising a transistor gate;
- and
- first and second ferroelectric capacitors individually having one capacitor electrode elevationally between the transistor gates of the first, second, third, and fourth transistors.
A memory cell comprising:
- first, second, third, and fourth transistors;
- and
- first and second ferroelectric capacitors individually comprising first and second capacitor electrodes having a ferroelectric capacitor insulator there-between, the first capacitor electrode comprising an elevationally-extending pillar, the ferroelectric capacitor insulator comprising an annulus radially outward of the first capacitor electrode, the second capacitor electrode comprising a portion radially outward of the ferroelectric-capacitor-insulator annulus.
A memory cell comprising:
- first and second laterally-spaced and elevationally-extending pillars;
- first and second ferroelectric capacitors individually comprising first and second capacitor electrodes having a ferroelectric capacitor insulator there-between;
- first, second, third, and fourth elevationally-extending transistors individually comprising source/drain regions, an elevationally-extending channel region between the source/drain regions and a transistor gate operatively proximate the channel region, the channel regions of the first and second transistors being laterally adjacent one another above the second capacitor electrodes;
- the channel regions of the third and fourth transistors being laterally adjacent one another below the second capacitor electrodes;
- the first pillar comprising the source/drain regions and the channel regions of the first and third transistors, the first pillar comprising the first capacitor electrode of the first ferroelectric capacitor;
- and
- the second pillar comprising the source/drain regions and the channel regions of the second and fourth transistors, the second pillar comprising the first capacitor electrode of the second ferroelectric capacitor.
4 more elements
25-38. (canceled)
Dependencies are inferred from the claim text.